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I am busy with some calculations regarding the components around the optocoupler and I am now finding myself in a bit of a mental struggle. I have done quite a lot of reading (at least here, here, here, this Vishay guide, this Toshiba guide and this Avago guide to name a few) and I still find myself unable to answer a few questions. The more I try to figure out the correct math, I just end up with more questions that need answers.

The application for this circuit is to isolate signals from mechanical switches on one power network (supply voltage of 5 V) to the inputs of a port expander IC on another power network. The optocoupler used in the design is the TLP621-4.

This is the circuit in question:

Circuit

Firstly, there is the input stage of the optocoupler. Designing for that seems to be rather straight forward – choose a suitable current to drive the LED at in order to switch on the phototransistor so that the correct logic voltage can appear at the pins of the port expander. The port expander runs at a supply voltage of 3.3 V, so the switch signals will also be translated/shifted to 3.3 V signals. Choosing a forward current of 5 mA corresponds to a \$V_f\$ of approx. 1.2 V at 25 °C, according to the datasheet.

For the LED this yields: \$R_{LED} = \frac{V_{supply} – V_f}{I_f} = \frac{5 – 1.2}{0.005} = 760 \Omega\$.

According to the optocoupler datasheet, \$I_f\$ = 5 mA corresponds to a CTR of 120%. Thus, the collector current \$I_C\$ = 5 mA \$\times\$ 120% = 6 mA. Now here comes my question – how do I design for the output stage of the optocoupler? If I want to convert the collector current to a voltage at the emitter so that the port expander can detect a logic HIGH/LOW, for what collector current and pull-down resistor values do I design?

Below follows the circuit as I have built it for testing purposes - it works. However, it is all nice that it works perfectly for this application so far, but it bothers me WHY it works:

Circuit with values

The LED current limiting resistor value is 10 kΩ, which yields a forward current of only \$I_f\$ = (5 – 1.2) / 10000 = 380 \$\mu\$A. The CTR curve in the optocoupler datasheet starts at approx. 75% at 1 mA, so the true CTR is probably below 70%. This yields a theoretical collector current of approx. \$I_C\$ = 380 \$\mu\$A x 70% = 266 \$\mu\$A. Furthermore, the pull-down resistor value at the output stage of the optocoupler is also 10 kΩ. Where does the collector-emitter voltage \$V_{CE}\$ come into play? If the output stage supply voltage is 3.3 V and the desired logic HIGH at the emitter is also 3.3 V, then this means that \$V_{CE}\$ must be 0 V - is this possible? If so, what do the various \$V_{CE}\$ - \$I_f\$ and \$I_C\$ - \$V_{CE}\$ curves in the datasheet mean?

I would appreciate it if someone could shed light on why the above circuit works and what the corresponding parameters are. Also, if the above design is not optimal, what would the correct approach be to designing the circuit for the mentioned desired specifications?

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A few notes:

  • CTR is only rarely a guaranteed value that you can use for accurate linear isolated measurements. In the case of the TLP621-4, the datasheet only guarantees that it's somewhere between 50% and 600%. I'm not sure where your 120% number came from. Even the graph on page 8 doesn't show 120% at 5 mA, and it has multiple very different lines from different sample devices besides.

  • That CTR curve (page 8) also shows CTRs down to 300 μA, so I'm not sure what datasheet you're looking at but it's not the one on the page you linked to.

  • This optocoupler is specifically marketed, and thus probably designed, as a solid-state relay, only intended to be used as a switch and not as an amplifier or analog isolator.

  • You won't be able to achieve a \$V_{CE}\$ of zero, as the output transistor still has a \$V_{CE,sat}\$ like any bipolar transistor. This doesn't matter, however, because there's a fair margin on what most logic chips and microcontroller inputs will accept as a logical high. It should say in the datasheet what that is, likely labelled as \$V_{IH}\$ (for voltage, input high).

  • What value you use for the output resistance also shouldn't matter, as long as it's high enough to allow the transistor to fully saturate, and low enough to reliably act as a pull-down on the logic input. When the transistor is saturated, CTR goes out the window, just like how β is useless in a standard BJT in saturation.

The way I would design this circuit is to have the LED run at a reasonable middle-of-the-range current, to ensure that the output transistor saturates regardless of what the CTR is. Since they guarantee the CTR to be at least 50% with a forward current of 5 mA, that's the condition I'd design for: 5 mA input, and 2.5 mA output. So choose your input resistor to give 5 mA through the LED.

Then, you need to select your output resistor. You are guaranteed that the output current will be at least 2.5 mA if you have no resistance in there at all. But we don't want that--we want to ensure that the transistor is saturated. So we use a resistance that, in combination with the transistor's \$V_{CE,sat}\$ (max 0.4 volts according to the datasheet), results in, let's say 2 mA current on the output.

Now, regardless of what the device's actual CTR is, you'll see an output current of approximately 2 mA through the resistor, and an output voltage of between 2.9 and 3.3 volts (depending on what the device's actual \$V_{CE,sat}\$ is). This is a voltage high enough for any 3.3 volt logic input I've ever worked with (and many, if not most, 5 V logic inputs too) to read it as a reliable high.


To answer your questions in the comments:

If the saturation voltage is a fixed value, then how does increasing (or decreasing) the resistor value not have an influence on \$V_O\$? Does the collector current compensate for the change in resistance, or am I missing something?

Yes, the collector current will reduce. One (oversimplified!) way to think of it is that (for complicated reasons relating to the way transistors work), it's not possible for there to be current through the transistor with \$V_{CE} < V_{CE,sat}\$.

Another intuition is to think of it this way: With the transistor powered from a 3.3 volt supply, with a 1 kΩ resistor in series with it, could that transistor possibly drive 10 mA through that resistor? That would make 10 volts across the resistor--but you only have 3.3 volts to work with! Clearly, it can't drive that much current, even if the CTR or β says that it should--this is when the transistor saturates.

Perhaps a follow-up question - what design condition drives the phototransistor into saturation in the first place? In other words, what are the design parameters to ensure that the phototransistor is in saturation?

An easy way to do it is as follows:

  • Either in a real circuit or in simulation (including manual circuit-solving as simulation, here), connect the collector to your supply voltage, and the emitter to ground. No resistors or anything.
  • Apply your designed current through the optocoupler's LED.
  • Measure or compute the current through the transistor.
  • Figure out a resistance that would produce that same current given that same supply voltage across it.

That resistance is (slightly higher than; we didn't account for saturation voltage) the minimum resistance required such that your transistor is in saturation. If you use a larger resistance, you will have less current, but still the same output voltage. If you choose a lower resistance, you will have the same current, and a lower output voltage.

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  • \$\begingroup\$ Thank you for your answer. It already clarified a few things for me that I was unsure of. I think my fundamental understanding of how the phototransistor works is somewhat flawed. In such a switching application, does one design for the specified saturation voltage (from the datasheet) by simply applying Ohm’s law together with summing the voltages? Would changing the pull-down resistor value not affect the saturation voltage? I have seen a lot of examples where the pull-down resistor is chosen as double the design value, and somehow the phototransistor is still saturated. \$\endgroup\$ – wave.jaco Apr 1 at 8:07
  • \$\begingroup\$ By the way, I have indeed looked at a different (wrong?) datasheet - docs.rs-online.com/0385/0900766b8162f85c.pdf. It baffles me how much this datasheet differs from the actual Toshiba one... \$\endgroup\$ – wave.jaco Apr 1 at 8:08
  • \$\begingroup\$ @wave.jaco Saturation voltage is (mostly) fixed for a given device when it's in saturation. Increasing the resistor will keep the device in saturation; decreasing it may allow it to leave saturation depending on the actual CTR of the device. \$\endgroup\$ – Hearth Apr 1 at 12:39
  • \$\begingroup\$ So in order to design for saturation I have to take the saturation voltage (0.4 V) and design the R value for \$I_C\$ (thus \$I_f\$ x CTR = 0.005 x 50% = 2.5 mA), taking into account \$V_{CE,sat}\$ in the voltage sum? Thus, \$V_o\$ = 3.3 – 0.4 = 2.9 V? If I calculate R for \$I_C\$, that gives me R = \$V_O\$ / \$I_c\$ = 2.9 / 0.0025 = 1160 \$\Omega\$. If the saturation voltage is a fixed value, then how does increasing (or decreasing) the resistor value not have an influence on \$V_O\$? Does the collector current compensate for the change in resistance, or am I missing something? \$\endgroup\$ – wave.jaco Apr 1 at 13:34
  • \$\begingroup\$ Perhaps a follow-up question - what design condition drives the phototransistor into saturation in the first place? In other words, what are the design parameters to ensure that the phototransistor is in saturation? \$\endgroup\$ – wave.jaco Apr 1 at 13:39
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The CTR is specified under optimal conditions to maximize the number, in particular Vce = 5V, Ta = 25°C and the optoisolator is brand new.

Depending on whether you buy the premium version or not, the CTR is guaranteed to be at least 50 or 100.

However your condition is not Vce= 5V, it's more like Vce < 1V. So, more realistically, use the datasheet saturated CTR numbers of 30 or 60%.

There are several other factors to consider- CTR typically drops about 25% as the temperature increases (see the typical curves). And the LED will age and become less bright as time passes (heavily affected by If and quality of LED). Toshiba is a top tier opto manufacturer, so probably the effect will be relatively small, but maybe allow 33% for that to be safe. So we can count on 0.30.005mA0.66*.75 ~= 750uA. So a load resistor of 4.7K or more should be okay.

Checking the typical dark current of 30uA maximum at 5V and 100°C we can establish a maximum of 20K for Voff < 0.6V. That's just a typical so we shouldn't use that directly, but a 50uA guarantee at 85°C is given by the datasheet so at 10K we'd be more than okay (provide Ta <= 85°C).

One more thing- speed. Toff typically varies from about 50us to about 150us as the load resistor varies from ~5K to ~20K. So, lower is better.

So 10K is a reasonable choice for the load resistor. It's possible to use a lower value such as 4.7K or 7.5K if you want a bit faster operation and/or guaranteed operation to higher temperatures. If you buy the premium version of the optocoupler you could approximately halve those values.

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  • \$\begingroup\$ Many thanks for your answer. As I have commented on Hearth's answer, I think my fundamental understanding on how the phototransistor works is somewhat flawed. The question I keep asking myself is - do you design for the specified saturation voltage using Ohm's law and summing of voltages? If so, how does it work that one can "choose" different values for the pull-down resistor and the phototransistor still remains saturated? All the individual design bits make sense to a great extent, but my problem lies in putting it all together and understanding the entire big picture behind the design. \$\endgroup\$ – wave.jaco Apr 1 at 8:20

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