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CONDITIONS:

  1. Output swing has to be at-least 80% of VDD (> 2.64 V in this case).
  2. Power supply rails available are VDD and ground only.
  3. Only one current source can be used in the design; IREF = 50 μA.
  4. Every bias voltage needed has to be generated by designing proper circuits.
  5. Use of resistors is not allowed in the design.
  6. Use a load capacitance of 1 pF on both the output terminals.
  7. ICMR should be 0.2 VDD to 0.8 VDD
  8. Phase margin has to be at-least 45°.

SPECIFICATIONS TO BE MET:

  • 3dB frequency in rad/sec = 10 k ±5%
  • Power dissipation (mW) = 3.0 ±5%
  • Current Gain = 35 ±5% dB
  • Voltage gain (Av in dB) > 45 dB

MY ATTEMPT: (I cascaded a CSA with a cascode amplifier in order to have higher swing at the out2 node)

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I am getting too large a current gain and a lower output swing than the required values for both of them. Also, 3 dB range isn't even available on the voltage gain (Vout2/Vin) plot.

What should I vary to obtain the required values?

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  • \$\begingroup\$ Just FYI, your PMOS bodies should be connected to their source, not VDD. Only NMOSes need to have their bodies connected to the substrate, PMOSes are inside another well and can have their source and body tied directly. \$\endgroup\$
    – Shredder
    Jan 2, 2023 at 22:19

1 Answer 1

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You cannot see your 3dB point because the bandwidth of your amplifier is much larger than what you're sweeping in frequency.

Also, your biasing is improper. M6 and M4 are just cascode devices and are there to provide a boost in the r_out. M8 however is a current source, just like M5 and M3. Therefore, the gate of M8 should be connected the diode generated by M5 as that is the actual current source. I would suggest that you use a wide swing cascode biasing instead.

The mirroring of M5 and M3 are far from optimal and you're not getting a proper current mirror based on W/L ratios. You're introducing a lot of error by biasing it that way. EDIT: At the moment, for biasing use ideal voltage/current sources and as many as you want until you get the results you want. After you meet your specs work on the bias separately as that won't affect your result at all provided it's a proper biasing scheme. In other words decompose the problem like below

enter image description here

Finally, for a gain of 45 dB (depending on the process technology you're using) I would say you can drop the cascode on M4 and play with the L's of M8 and M9. I could draw it for you but I'm assuming this is a homework/project problem for school :)

Be sure to understand all the trade-offs here. These will come in handy on job interviews as interviewers ask exactly how to fix circuits like these.

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  • \$\begingroup\$ Thanks a lot! A few points- 1)"You cannot see your 3dB point because the bandwidth of your amplifier is much larger than what you're sweeping in frequency." - Yes I know I will have a 3dB point at very high frequency but what is required is only 10 K± 5%, so please suggest how can I achieve that. 2)" Therefore, the gate of M8 should be connected the diode generated by M5 as that is the actual current source"- I actually did that but the swing is much less(in mV) than required(>2.64V).Please suggest how can swing be increased keeping voltage gain above 45 dB \$\endgroup\$
    – Manan01
    Apr 1, 2021 at 11:32
  • \$\begingroup\$ Also , 3)"I would suggest that you use a wide swing cascode biasing instead."- I am restricted to only use 1 current source of 50uA and this actually fixes the bias part on the left and moreover I'm not familiar with this topology. \$\endgroup\$
    – Manan01
    Apr 1, 2021 at 11:32

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