# Confused with the output resistance of the CMOS inverter

I'm currently reading about the CMOS inverter from Rabaey Chandrakasan Nikolic - Digital Integrated Circuits 2nd Ed, it states:

I'm okay with the first part, but I'm not sure if I totally understand what it does imply (starting from therefore), in conciseness:

1- How does a path existing with finite resistance between the output and supply or ground help with the low output impedance?

2- What does it mean for the inverter (a digital circuit) to have low output impedance? In analog circuits like the common-source/common-drain amplifier it meant that it can drive heavy loads (e.g. a large capacitance or at high frequency)

3- How does it help make it less sensitive to noise and disturbances?

I have one more question that I would be also happy if I get the answer to, the book also states that because the high and low output levels are equal to supply and ground voltage respectively, we know that it has a high noise margin, does knowing the fact about output voltage levels alone help us talk about the noise margin because I don't it feel that it says enough?

Thank you :)).

"What does it mean for the inverter (a digital circuit) to have low output impedance?"

Inverters has 2 output states:

1. Vout ≅ VDD (logic 1)

or

1. Vout ≅ GND (logic 0)

Hypothesis: Vout ≅ VDD

Attach a resistor R to Vout.

R will draw current out of Vout.

Low output impedance mean that you can lower R as much as you want (*) without Vout dropping.

(*) Within certain limits

Example:

Vout = 3 V

R = 30 Ohm

If the inverter has 0 Ohm output impedance, than it will be able to deliver 100 mA to the load R and Vout will remain at 3 V.

If the inverter has 10 Ohm output impedance, than it will able to deliver 75 mA to the load R but Vout will now drop to 3 * (3 / 4) = 2.25 Volt.

Output circuits stages are designed to show low output impedance in order to set/impose the output voltage to the load.