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I'm actually designing a circuit that would permit me to drive a Smartcard, it's a pretty straight forward design : enter image description here

All the signal starting with CA are coming from GPIO of an IC that controls all the timings, and the signal starting with SC are the one going to the smartcard. It's just simple level shifters +3.3 to +5V.

The level shifter for the DATA and RST are working really well. However, the CLK one has some issues. I have a perfectly fine CLK on the 3.3 side, but on the 5V side I have this: enter image description here

As you can imagine the card can't handshake because the signal doesn't reach the level I want too. I don't understand the problem because all the lines are exactly the same and if I refer to the datasheet of my transistor the timings are perfectly fine to handle my 3.6 MHz clock, also if it was a timing issue I assume my clock signal wouldn't look like a square signal like that.

Does anyone has an idea of where it could come from ?

I also ordered a transistor with a lower Rdson and faster switching frequency i'll update you on that matter

PS:

enter image description here

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  • \$\begingroup\$ What happens if you feed the clock signal through one of the other circuits? \$\endgroup\$
    – Hearth
    Commented Apr 2, 2021 at 13:22
  • \$\begingroup\$ I tried to invert, and the same thing happens \$\endgroup\$ Commented Apr 2, 2021 at 13:23
  • \$\begingroup\$ What do you mean by invert? \$\endgroup\$
    – Hearth
    Commented Apr 2, 2021 at 13:24
  • \$\begingroup\$ Oh yeah sorry I translate from my mother tongue, when I say invert I mean I put the 2 CLK signals on the circuit meant for DATA and the 2 signals meant for DATA on CLK \$\endgroup\$ Commented Apr 2, 2021 at 13:26

1 Answer 1

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if I refer to the datasheet of my transistor the timings are perfectly fine to handle my 3.6 MHz clock

But you have a bunch of 10 nF capacitors on your data/clock lines: -

enter image description here

A 10 nF capacitor at 3.6 MHz has an impedance of 4.42 Ω and that's going to wreck clock and data signals.

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  • \$\begingroup\$ I'm sorry I should have added that those capacitor were not connected, they are hzre just in case for my pcb design. \$\endgroup\$ Commented Apr 3, 2021 at 6:48

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