How to view a detailed resource utilization report on an FPGA design when implementation fails in Xilinx Vivado?

Question

I'm using Xilinx Vivado 2020.2 on Windows 10.

When I attempt to generate a bitstream, it fails at implementation with this error:

So I need to reduce the number of FDCE cells I'm using. That's doable, but I need to know where they are. The synthesis report only tells me the total number of FDCE cells used across the design, not a per-module breakdown.

I can usually use the utilization reports produced in the implementation stage to see where resources are consumed, but since implementation failed, the "Report Utilization" option is greyed out.

Implementation got far enough to know I'm using too many FDCE cells for my target device, so how can I see where they're being used?

Answer 1

The Xilinx support page has a Q/A for this: Vivado - How to get resource utilization of one sub module?

When button to get the utilization report is greyed out, you can't get to the reports via the nice GUI. But you can still have it dumped to a file using the TCL console command:

report_utilization -hierarchical -file path_to_output_text_file

Navigate to the output file you specified and you'll see a nice hierarchical resource utilization report.