After discussions in the comments, I've realised that the only way to do this for full-duplex is to use a switching IC.
Also, I mean simplex, not half-duplex for option 1. That is, the FPGA is only receiving packets, not sending them.
I've been looking to implement ethernet in a daisy-chain configuration on my board.
- low cost
- latency through board < 8us
Nice to have requirements:
- full duplex
- as few IO pins to the FPGA as possible
Options after a bit of research:
Option 4 was the first thing I thought of, but is the worst at meeting my specs. Options 1 or (ideally) 2 would meet my requirements, as long as I get the implementation right.
Can the RGMII interface be used in this way? I guess is the first question. If not, then I'll probably have to go with option 1 and call it a day.
I'm quite sure that option 1 would work, however I would really like full duplex. It's not hugely necessary, but a very good nice-to-have. Are there any suggestions as to how to handle the arbitration re option 2? Is it possible to do something like that using the FPGA?
Option 3 is out purely because multiple boards are going to be daisy chained and the diodes attenuate the data lines too much.
I'm also not really looking at switch ICs due to cost. If it's possible to find one below $5 or so then it's within budget and probably considerable, but I doubt that's the case.
Also re < 8us latency through board: I calculated this spec based on system requirements, and I think it's possible since a 125 Mhz clock has a period of 8ns, so 8us is 1000 clk cycles of RGMII, plus a latency of 1.5us through each PHY, seems like enough for options 1 - 3. option 4 goes through the FPGA which makes things a bit more complicated (latency through TEMAC, etc), although I can't imagine even the temac latency is too long.