After discussions in the comments, I've realised that the only way to do this for full-duplex is to use a switching IC.

Also, I mean simplex, not half-duplex for option 1. That is, the FPGA is only receiving packets, not sending them.

I've been looking to implement ethernet in a daisy-chain configuration on my board.

Hard requirements:

  • 1000BASE-T
  • low cost
  • latency through board < 8us

Nice to have requirements:

  • full duplex
  • as few IO pins to the FPGA as possible

Options after a bit of research: options

Link for full size pic

Option 4 was the first thing I thought of, but is the worst at meeting my specs. Options 1 or (ideally) 2 would meet my requirements, as long as I get the implementation right.

Can the RGMII interface be used in this way? I guess is the first question. If not, then I'll probably have to go with option 1 and call it a day.

I'm quite sure that option 1 would work, however I would really like full duplex. It's not hugely necessary, but a very good nice-to-have. Are there any suggestions as to how to handle the arbitration re option 2? Is it possible to do something like that using the FPGA?

Option 3 is out purely because multiple boards are going to be daisy chained and the diodes attenuate the data lines too much.

I'm also not really looking at switch ICs due to cost. If it's possible to find one below $5 or so then it's within budget and probably considerable, but I doubt that's the case.

Also re < 8us latency through board: I calculated this spec based on system requirements, and I think it's possible since a 125 Mhz clock has a period of 8ns, so 8us is 1000 clk cycles of RGMII, plus a latency of 1.5us through each PHY, seems like enough for options 1 - 3. option 4 goes through the FPGA which makes things a bit more complicated (latency through TEMAC, etc), although I can't imagine even the temac latency is too long.

  • \$\begingroup\$ Do you need the fpga application to send packets as well (or is it just sniffing)? If yes, only up the chain or both ways? Does the fpga app. need to read packets both ways of the chain? BTW, option 1 looks like simplex rather than half-duplex. \$\endgroup\$ Commented Jan 23, 2013 at 4:58
  • \$\begingroup\$ In any case, the arbitration you refer to would be at the mac level IMO, not at the rgmii level, so if you need to read/write in both directions the two MACs are required anyway. \$\endgroup\$ Commented Jan 23, 2013 at 5:01
  • \$\begingroup\$ I mean the FPGA doesn't have to send packets, only receive. Time to google the difference between half duplex and simplex. \$\endgroup\$
    – stanri
    Commented Jan 23, 2013 at 5:10
  • \$\begingroup\$ Receive only packets coming down the chain? If that is the case, option 1 should work, and the PHYs can be connected together in full duplex (not simplex). The bad news is that the FPGA won't be able to send any kind of acknowledgement. \$\endgroup\$ Commented Jan 23, 2013 at 5:31
  • \$\begingroup\$ You're basically just sniffing packets coming in one direction. \$\endgroup\$ Commented Jan 23, 2013 at 5:39

2 Answers 2


EtherCAT is designed as a very low-latency Ethernet - it's not a direct daisy-chain, but passes through the controller. As the bits pass by, the controller updates the ones which need to be changed by the data it is transmitting before handing them back to the PHY.

Some operational details and a picture of how it works are here


1000BaseT cannot be daisy chained. If you want daisy chain, use 10Base2 (thinnet) or 10Base5 (thicknet).

1000BaseT can be used in star topology and would need a bridge between nodes.

  • \$\begingroup\$ I'm not sure about this. Could you explain why? The board I'm designing is based on another product which (as far as I know) daisy chains 1000BASE-T. Are you saying that it can't be daisy chained in full duplex, or can't be daisy chained in full and half? \$\endgroup\$
    – stanri
    Commented Jan 23, 2013 at 4:29
  • 1
    \$\begingroup\$ @stanri I would like to recommend to you to read more about various Ethernet PHYs before you plan to implement. You have not provided enough information in your question. \$\endgroup\$ Commented Jan 23, 2013 at 4:35
  • \$\begingroup\$ Could you point me in the right direction in terms of what info I need to provide or what else I need to know? \$\endgroup\$
    – stanri
    Commented Jan 23, 2013 at 4:36
  • \$\begingroup\$ @stanri - If you have an existing device that supports daisy-chaining, it probably has a internal 1000 BASE-T switch internally, to make it look like it's daisy-chained. \$\endgroup\$ Commented Jan 23, 2013 at 4:40
  • \$\begingroup\$ @stanri I'm not a FPGA expert. Various IP (intellectual properties) are available for FPGAs as modules. Please check with your FPGA provider what IPs they offer related to Ethernet. \$\endgroup\$ Commented Jan 23, 2013 at 4:40

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