# ADC Chip Timing Question

When is the best time to read the bit out of a serial data output 12-bit ADC chip. The chip is a AD7476A, and here is the datasheet AD7674A Datasheet.

Going by the timing diagram, when is the best time to read the output bit during the SCLK clock, the falling or rising edge? I think the falling edge of each clock cycle from 4 to 15 should give the 12 valid data bits out provided the timing is correct?

Below is an image from the datasheet of the timing diagram, with the description of the serial interface.

EDIT 1

Thought I would provide an update as to my development of the timing to read data from this ADC chip. I have simulated my code with a testbench and the waveform diagram can be seen below. I continuously clock the ADC chip SCLK pin at 10 MHz as you can see. I shift the data input into the shift register on the rising edge of the SCLK clock, and after 16 clock cycles when CS goes low, I store the 12-bit register value into another register on the falling edge on clock cycle 16. Then on the next rising edge I bring CS high again and this repeats.

The next two images show the design being implemented on hardware, although as I haven't got the ADC chip yet, I am testing with the pin either pulled high or grounded. You can see the two images reading either 4095 or zero with the 12 LEDs on the board representing the stored shift register value at all times.

I will provide an update when I get the chip as it will be probably take a bit of testing to get it to work.

EDIT 2

Ok so I have connected the ADC chip to the FPGA with the CS, SCLK and SDATA pins. The FPGA is powered with 5V and the on board 3.3V from the FPGA powers up the ADC chip circuitry. I m reading the 12 bit output from the chip on a 7 segment display.

First attempt sort of works. However when I turn the pot to low (or 0V analog input to ADC chip, the result is 103. Something weird happens as I turn the pot up. Once I reach halfway pot position, the 12 bit value is 4060 and once I go past that the the ADC value jumps back to zero.

Then as I continue to turn the pot up to the max position (3.3V input to ADC chip), the 12 bits are around 4000.

Any reason as to why this jump back to zero. The bits don't seem to increase by 1, but maybe 6 or so, although it is impossible to turn the pot so finely.

Where would you folks start to debug this? I have a power supply arriving tomorrow so I can input exactly between 0V and 3.3V to see the LSB changes to make sure my interfacing is ok.

• Typical SPI mode-3 timing. SCLK idle at 1, slave/master launches data at negative edges, master/slave samples at rising edges. Apr 4 at 11:55
• @MituRaj That is good to know, thank you. Apr 4 at 12:30

## 2 Answers

Here's a good clue: -

And, if you look at the value for $$\t_4\$$ it is quoted here: -

So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the falling edge of SCLK to read valid data.

Of course, if you look at $$\t_7\$$ it tells you that current data is valid for maybe 7 ns should you attempt to read it but, in all honesty, I'd use the rising edge of SCLK.

Also $$\t_6\$$ tells you that the SCLK minimum pulse width at full speed (20 MHz) is 20 ns so, it looks like the positive edge is the one to use.

• Ok, so the main thing is that the timing diagram is not to scale, and the timing figures are key to this? Apr 4 at 10:58
• @David777 you have to use the timing numbers to properly make sense of the timing diagram. Sometimes, on complex chip timings I copy the numbers onto the timing diagram so I can make better sense of things. Apr 4 at 11:01
• @David777 look at $t_2$. Apr 4 at 11:08
• There is no maximum time for $t_2$ as far as I can see. Apr 4 at 11:14
• The rising edge of SCLK does not invoke $t_8$ so yes, you will read the last bit providing you don't let SCLK fall too early Apr 4 at 11:23

The safest time to capture data is ... immediately before the SCLK falling edge.

If you are rolling your own SDI interface, you can arrange this any way you like.

It is tempting to capture data on the positive SCLK edge ... but...

with the maximum SCLK frequency of 20MHz, an SCLK period of 50 ns assures the SCLK rising edge is 25 ns after the falling edge. This is less than the maximum SCLK-out time, but there is no specified minimum SCLK-out time, and thus no guarantee whether you read old data, new data, or a signal in transition (with possible metastable outcomes).

If you restrict SCLK to 10MHz or less, then you can safely use the rising SCLK edge to sample data.

But with SCLK= 20MHz (or any lower rate), where you are generating SCLK, sample the incoming data on the same VHDL delta cycle that generates SCLK falling edge. Then the SCLK output buffer delay > 0, guaranteeing data remains stable until after you have sampled it. You must also constrain that output buffer delay to be < 10 ns minus input buffer delay, to guarantee data arrives before the next falling SCLK edge.

• Provided an update to my progress if you are interested. I used SCLK at 10MHz to use the rising edge of the SCLK to shift in data. Apr 5 at 19:10
• I have an update if you are still happy to help. Apr 8 at 18:21
• Update sounds as if you're reading Bit 10 as if it was Bit 11 (MSB). Apr 8 at 22:33
• Yeah I thought that initially, but it seems to read the right value now. Take a look at the last comment I left in the answer above if you have time. Apr 8 at 22:42