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I want to generate a negative voltage from a possitive rail. To do so, I'm reading this article. Here is the schematics it is depicting, assument the input step is +10V: enter image description here

I understand that when the capacitor is charged, there will be a potential difference of 9.7V, since the first plate is at 10V and the second one needs to be at 0.7 because of D1.

However, the text also says:

When the positive plate drops rapidly from 10V to 0V, this 9.3V potential difference must be maintained due to coupling. Therefore, the negative plate drops to -9.3V.

I don't get that. My understanding is that if the voltage in the first plate drops sharply to 0V, C1 won't discharge through D1, because D1 won't be forward biased when its anode goes below 0.7V. Therefore, those 0.7V should discharge through the former C1 positive plate, which is now at 0V (so GND).

How is that the negative plate drops to -9.3V? how is that possible if D1 is supposed to force its anode to be at +0.7V with respect to ground?

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2 Answers 2

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The only path for C1 to discharge is for current to flow through D2, which applies a negative charge to C2. If you're having difficulty with this, first visualise what is happening to C1 in isolation - it's charged to 9.3V and the positive plate is then connected to ground, so the negative plate will be at -9.3V. Once you're happy with that, see how the rest of the circuit will behave.

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I think @Frog's accepted answer gives the right qualitative answer. If it helps to have a simulation, here you go:

schematic

simulate this circuit – Schematic created using CircuitLab

Running the simulation above produces the following plot:

negative voltage generator simulation

The current plots through each diode are particularly instructive. Observe:

  • On the rising edge of V(in), only D1 conducts, charging C1.
  • On the falling edge of V(in), only D2 conducts, rebalancing charge from C2 to C1.

I think a helpful way to think about this circuit is to remember that the capacitor's stored charge (and hence stored voltage difference) is something that cannot change instantly. It requires current to flow over time to charge or discharge. So even as V(in) switches "instantly" from 0 to 10 or vice-versa, the relative voltage difference across the capacitor remains constant at the instant of the step.

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