What are the structural differences between Serial NOR Flash and Parallel NOR Flash? If there is a structural difference , then What are the differences between Serial NOR Flash and Serial NAND Flash? I can't seem to get the resource for this particular question from Googling
Serial flash uses serial bus to write and read the data from the device. Popular serial buses include I2C and SPI. Serial signaling involves address, data and control signals on 2-3 wires.
Parallel flash uses parallel 8 Bit I/O or Bus to write and read the data from the device. Parallel signals needed are Data bus (usually 8 bit), address bus (depends on device density) and control bus (en, oe).
I could have added more details but the question is too generic, hence generic answer.
Wikipedia: Flash memory has a pretty good explanation of the structural difference between NOR flash and NAND flash.
-- NAND flash
Both kinds of Flash memory use floating-gate transistors. To read out a word, other stuff on the flash chip drives the selected word line to a "small" positive voltage. When the floating gate is charged with electrons, it shields the transistor from the word line enough that the transistor stays OFF. So the resistor pulls the bit line HI, and the CPU sees a one (1) bit. When the floating gate is erased, even that "small" positive voltage on the word line is enough to turn ON the transistor and pull the bit line to LO, overpowering the resistor, and the CPU sees a zero (0) bit.
NOR flash connects those transistors in a NMOS NOR gate. To avoid interfering with the selected word line, other stuff on the flash chip sets the non-selected word lines to GND (turning their transistors off).
NAND flash connects those transistors in a NMOS NAND gate. To avoid interfering with the selected word line, other stuff on the flash chip sets the other word lines to a "larger" positive voltage (turning their transistors on).
The pull-down path from the bit line to GND goes through many transistors in a NAND flash. The pull-down path goes through only one transistor in NOR flash. So NOR flash can be significantly faster than NAND flash (when built from equivalent transistors). (But even NAND can be faster than a spinning hard drive).
As you can see from the purple chip cross-section, the NOR flash requires many more contact vias from the bit line down to the transistors. Because NAND flash does not need those vias, the physical layout of NAND can be packed significantly less area per bit. So NAND flash can cost significantly less than NOR flash (per bit, and when built from equivalent transistors). (But even NOR flash costs less per bit than DRAM).
Both parallel and serial off-chip interfaces are possible with either NAND or NOR flash.
Execute-in-place applications (XIP) execute directly out of Flash. All the bits of the instruction need to be fetched every instruction cycle, so such applications tend to use parallel NOR flash.
Solid-state disks (SSDs) tend to use parallel NAND flash chips.
Flash configuration memories are usually serial Flash chips. I think I've seen both serial NOR flash and serial NAND flash in this application.
(The pull-up is usually not a literal resistor. The details didn't seem relevant here.)
I don't know what you mean by structural - if you mean the internal structure, I have no idea.
Yet, the main difference between serial and parallel NOR flash is the way the memory is accessed. Serial NOR Flashes are accessed via SPI, therefore having a low pin count whereas parallel NOR flashes are accessed via the usual data/address bus.
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