When running LTSpice simulations on forward biased diodes I get plots like the following:
I am wondering if there is a reason for this huge difference in current given that the Silicon diodes should obey more or less the same principles in the "sub-threshold" region ?! Or is this only an inaccuracy in the models ?
I have read about the Shockley Diode equation which predicts an exponential dependence. In Spice the V-I dependence is linear below about a few 10s of mV. Is this accurate ?
I am interested in this regime of operation as I want to use antiparallel diodes to clamp a fault voltage of a node to within +/- 1 V of another node, but present as little leakage as possible (pA) between the two nodes in normal operation, where both nodes are within about 1 mV of each other.
I realized now, that the Shockley equation does indeed predict the linear region for \$|V_D|\ll V_T\$. Thanks to Enrico's answer I became aware of the large differences in Diode Reverse Saturation Current that determines the leakage in this bias regime.
For my application, I need a low leakage, but also large current capability for a few µs in the fault case. After comparing several diodes, it looks like unidirectional ESD diodes are best for this job. They will clamp in forward direction to about 1 V, so antiparallelling two of them does a good job. Their actual Zener Voltage does not matter in this application, so one could use whatever is on hand. Their leakage is also much better than rectifier diodes with a similar current rating. The latter seem to favor low forward drop.
There was also the comment of just measuring it. I will try to add results, if I still remember when I get around to visit the lab and find the time.