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I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the path to the asynchronous clear port.

Reset synchronizer

Constraint:

set_max_delay -to [get_pins -hierarchical *i_reset_bridge*|s_rst_sync_FF[*]|ACLR] 10.000

Quartus tells me that it cannot find any matching pins:

Argument <to> is an empty collection

Any hint on how to get my sdc running?

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  • \$\begingroup\$ This will be FPGA and tool dependent. \$\endgroup\$
    – user16324
    Apr 6, 2021 at 14:07
  • \$\begingroup\$ Intel MAX 10, Quartus Prime 18.1 \$\endgroup\$
    – Juergen
    Apr 6, 2021 at 14:09
  • \$\begingroup\$ This reset bridge synchronises only the de-assertion of the async reset, the reset-assertion to your design is still asynchronous. Is your design using a global asynchronous reset? Just to confirm your intent. \$\endgroup\$
    – Mitu Raj
    Apr 6, 2021 at 18:46
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    \$\begingroup\$ @MituRaj Yes, assertion can cause metastability. But the reset pulse is stretched by the reset bridge to allow enough time for the metastability to settle. \$\endgroup\$
    – Juergen
    Apr 7, 2021 at 6:54
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    \$\begingroup\$ Something like: set_max_delay -from [get_cells flopA] -to [get_cells flopB] 2 ; you will get the full hierarchial name of flopA and flopB from schematic/netlist. \$\endgroup\$
    – Mitu Raj
    Apr 7, 2021 at 10:27

1 Answer 1

Reset to default
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My constraints now look like this:

set_max_delay -to [get_pins -nocase -hierarchical s_rst_sync_ff[*]|CLRN] 10.000
set_max_delay -from [get_cells -nocase -hierarchical s_rst_sync_ff[*]] -to [get_cells -nocase -hierarchical s_rst_sync_ff[*]] 2.500

Besides, I enabled synchronizer identification in the Quartus qsf file:

set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"

With these settings, the design meets timing and all synchronizer flops are placed close together.

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  • \$\begingroup\$ The first statement is not actually needed on CLRN, as an asynchronous assertion doesn't need to be constrained on sdc, only de-assertion by the synchronizer has to be. By the way, Is" s_rst_sync_ff" the name of the synchronizer module instance? What's the need of -nocase/hierarchial? Just wondering. \$\endgroup\$
    – Mitu Raj
    Apr 7, 2021 at 10:38
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    \$\begingroup\$ @MituRaj The VHDL signal s_rst_sync_ff is a std_logic_vector based shift register. It's the synchronizer flop chain. \$\endgroup\$
    – Juergen
    Apr 7, 2021 at 10:41
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    \$\begingroup\$ @MituRaj hierarchical is needed because I have multiple instances of the reset bridge in different module at different hierarchy levels in my design. nocase could be omitted I guess. \$\endgroup\$
    – Juergen
    Apr 7, 2021 at 10:42
  • \$\begingroup\$ Cheers mate ... \$\endgroup\$
    – Mitu Raj
    Apr 7, 2021 at 10:42
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    \$\begingroup\$ @MituRaj thx a lot! \$\endgroup\$
    – Juergen
    Apr 7, 2021 at 10:43

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