I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the path to the asynchronous clear port.
set_max_delay -to [get_pins -hierarchical *i_reset_bridge*|s_rst_sync_FF[*]|ACLR] 10.000
Quartus tells me that it cannot find any matching pins:
Argument <to> is an empty collection
Any hint on how to get my sdc running?