# How to make a register in VHDL remember?

I was given the assignment to implement an 18-bit register in VHDL. I used an example from the book "Free Range VHDL" recommended to me earlier. Here's what I got:

library IEEE;
use IEEE.std_logic_1164.all;

entity reg18 is
port ( REG_IN  :  in std_logic_vector(17 downto 0);
LD,CLK  :  in std_logic;
REG_OUT : out std_logic_vector(17 downto 0));
end reg18;

architecture reg18 of reg18 is
begin
reg: process(CLK)
begin
if (rising_edge(CLK)) then
if (LD = '1') then
REG_OUT <= REG_IN;
end if;
end if;
end process;
end reg18;


However, the mentor argued that it doesn't remember the input and something with the VHDL signal must be done. Nevertheless, here's a citation from the same book:

If you have not speciﬁed what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By deﬁnition, if the input changes to an unspeciﬁed state, the output remains unchanged. In this case, the output associated with the previous set of input can be thought of as being remembered. It is this mechanism, as strange and interesting as it is, that is used to induce memory in the VHDL code.

Can you, please, explain to me how the mechanism of remembering in VHDL really works? Thank you in advance.

EDIT: By signal was meant the VHDL signal that is opposed to the variable. And yes, your comments confirm the citation.

• the mentor argued that it doesn't remember the input and something with a signal must be done - this statement is not clear. The code does produce an inferred latch, and the previous value of REG_OUT will be "remembered" if LD is not 1. Apr 6, 2021 at 18:44
• For me your code seems correct, or maybe a part of the exercise is missing. Apr 6, 2021 at 18:48
• Hmm, but isn't it the only job of a register? To "remember"? Apr 6, 2021 at 19:05
• Take a step back from VHDL and understand digital logic circuits. The electronic circuits came first. Afterwards came the attempt to simulate their behaviour using a Hardware Descriptor Language. VHDL is simply an elaborate, up-market netlist. (And avoid confusion by seeing clearly that it is not - not - a programming language.) So: first learn your digital logic circuits. In this case, it's a D-type Flip-Flop (DFF). Understand clearly how that circuit 'remembers' or stores a data bit. Once you understand that clearly, the circuits that VHDL implies by behaviour may make a lot more sense. Apr 6, 2021 at 19:12
• The output won't change from its existing state if LD is not '1' on a rising clock edge. You could argue that the state of REG_OUT is unknown, but it's certainly remaining static. Apr 6, 2021 at 19:51