I was given the assignment to implement an 18-bit register in VHDL. I used an example from the book "Free Range VHDL" recommended to me earlier. Here's what I got:

library IEEE;
use IEEE.std_logic_1164.all;

entity reg18 is
    port ( REG_IN  :  in std_logic_vector(17 downto 0);
           LD,CLK  :  in std_logic;
           REG_OUT : out std_logic_vector(17 downto 0));
end reg18;

architecture reg18 of reg18 is
    reg: process(CLK)
        if (rising_edge(CLK)) then
            if (LD = '1') then
                REG_OUT <= REG_IN;
            end if;
        end if;
    end process;
end reg18;

However, the mentor argued that it doesn't remember the input and something with the VHDL signal must be done. Nevertheless, here's a citation from the same book:

If you have not specified what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By definition, if the input changes to an unspecified state, the output remains unchanged. In this case, the output associated with the previous set of input can be thought of as being remembered. It is this mechanism, as strange and interesting as it is, that is used to induce memory in the VHDL code.

Can you, please, explain to me how the mechanism of remembering in VHDL really works? Thank you in advance.

EDIT: By signal was meant the VHDL signal that is opposed to the variable. And yes, your comments confirm the citation.

  • \$\begingroup\$ the mentor argued that it doesn't remember the input and something with a signal must be done - this statement is not clear. The code does produce an inferred latch, and the previous value of REG_OUT will be "remembered" if LD is not 1. \$\endgroup\$
    – Eugene Sh.
    Apr 6, 2021 at 18:44
  • 1
    \$\begingroup\$ For me your code seems correct, or maybe a part of the exercise is missing. \$\endgroup\$
    – Grabul
    Apr 6, 2021 at 18:48
  • 1
    \$\begingroup\$ Hmm, but isn't it the only job of a register? To "remember"? \$\endgroup\$
    – Mitu Raj
    Apr 6, 2021 at 19:05
  • \$\begingroup\$ Take a step back from VHDL and understand digital logic circuits. The electronic circuits came first. Afterwards came the attempt to simulate their behaviour using a Hardware Descriptor Language. VHDL is simply an elaborate, up-market netlist. (And avoid confusion by seeing clearly that it is not - not - a programming language.) So: first learn your digital logic circuits. In this case, it's a D-type Flip-Flop (DFF). Understand clearly how that circuit 'remembers' or stores a data bit. Once you understand that clearly, the circuits that VHDL implies by behaviour may make a lot more sense. \$\endgroup\$
    – TonyM
    Apr 6, 2021 at 19:12
  • \$\begingroup\$ The output won't change from its existing state if LD is not '1' on a rising clock edge. You could argue that the state of REG_OUT is unknown, but it's certainly remaining static. \$\endgroup\$
    – akohlsmith
    Apr 6, 2021 at 19:51

1 Answer 1


One possibility is that your mentor is considering that signal declarations are needed to provide the "storage" for the register. Just as an example, they are declared in this document from Xilinx:

enter image description here

The flip-flops are not synthesized because of the signal declarations. It is the edge triggered part of the code you have shown that implies the flip-flops, regardless of the fact that they handle inputs and outputs directly.

As you can see, the synthesis of your code (using Vivado) correctly results in a series of d-flip-flops:

enter image description here

Additionally, take a look at this question and the 2 up-voted answers.

  • \$\begingroup\$ Ah, I think I'm starting to understand. REG_IN and REG_OUT are just the ports of the register, while the actual storage is the signals. Am I right? If so, I still don't understand why do we need 2 signals. From my current perspective it seems logical to me to write from REG_IN to the newly introduced signal on rising edge and remove REG_OUT from the code completely. \$\endgroup\$ Apr 6, 2021 at 21:32
  • \$\begingroup\$ No. I'm sorry. I meant exactly the opposite. 'signals' do not provide storage like if VHDL was a programming language. As shown above your code correctly infer the flip-flops without the signals. And don't worry. It is a different paradigm to get used to if you come from a software background. HDLs describe hardware, as the name implies. The book is correct! \$\endgroup\$
    – devnull
    Apr 6, 2021 at 21:34
  • \$\begingroup\$ Thank you! And what the signals were for in the link you provided in the end? Or just forget about them? \$\endgroup\$ Apr 6, 2021 at 21:42
  • \$\begingroup\$ You are welcome. The answers (and comments) in the question linked at the end show precisely that: forget about the signals in this case. "Modern" tools will handle this just fine. \$\endgroup\$
    – devnull
    Apr 6, 2021 at 21:46

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