I was given the assignment to implement an 18-bit register in VHDL. I used an example from the book "Free Range VHDL" recommended to me earlier. Here's what I got:
library IEEE; use IEEE.std_logic_1164.all; entity reg18 is port ( REG_IN : in std_logic_vector(17 downto 0); LD,CLK : in std_logic; REG_OUT : out std_logic_vector(17 downto 0)); end reg18; architecture reg18 of reg18 is begin reg: process(CLK) begin if (rising_edge(CLK)) then if (LD = '1') then REG_OUT <= REG_IN; end if; end if; end process; end reg18;
However, the mentor argued that it doesn't remember the input and something with the VHDL signal must be done. Nevertheless, here's a citation from the same book:
If you have not speciﬁed what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By deﬁnition, if the input changes to an unspeciﬁed state, the output remains unchanged. In this case, the output associated with the previous set of input can be thought of as being remembered. It is this mechanism, as strange and interesting as it is, that is used to induce memory in the VHDL code.
Can you, please, explain to me how the mechanism of remembering in VHDL really works? Thank you in advance.
EDIT: By signal was meant the VHDL signal that is opposed to the variable. And yes, your comments confirm the citation.