sub-kilohertz channel spacing with PLL

Question

So I'm trying to use one of Analog's evaluation board PLL circuits (ADF4350, here). I need to generate frequencies around 1 GHz, ideally in a +/- 250 MHz range, but in steps of < 1 KHz.

Using the ADF4350 evaluation board, I'm able to specify (say) 0.5KHz between channels. But, I notice that (for example) it is able to produce a really nice, clean 1000 MHz signal, but stepping it to (ie) 1000.001 MHz produces symmetric sidebands that are about -30 dBc and spaced about 1 KHz from the center frequency. It doesn't make a difference whether I'm in low noise or low spur mode.

Has anyone experienced a similar problem? I'm wondering if it's worth trying to custom design something with a different loop filter, or if I should start looking around for other options. This is going to be used in locking electronics for a very narrow line-width laser, and sidebands like that will almost certainly broaden the line :/

Answer 1

It looks like the ADF4350 creates "fractional" multipliers by dithering the divider ratio in the feedback path. It is this dithering that is creating your sidebands.

A better approach would be to keep the '4350 in an integer mode all the time, and instead use one of their DDS chips to generate the reference for it.

Answer 2

I think Dave Tweed nailed down the reason for the spurs you're seeing.

An alternate solution that could be lower cost than Dave's suggestion:

• Use a 10 MHz crystal oscillator, ovenized if necessary, to provide long term stability.

• Use a DDS chip at, say, 125 MHz to provide adjustability

• Feed the DDS output to a x8 multiplying PLL to bring up the output frequency to 1 GHz and filter out any DDS artifacts. (Whether a integer-N or fractional-N multiplier will be better to minimize spurs is something you'll have to think about, or maybe someone else will chime in on).

For the final DDS stage, using the narrowest-tuning VCO you can find to cover your frequency band will help to minimize phase noise. As of course will careful attention to the loop filter design.

Answer 3

It looks like the 4350 eval board is set up for a 20 kHz loop filter Bandwidth, so it's not a surprise that you're seeing fractional n spurs within that bandwidth. There's a couple of potential solutions.

If you replace the Reference oscillator with a DDS, then that will help you with the frequency resolution. However, you'll need to be careful that the DDS doesn't have DAC output spurs that show up on your output. I'd follow the DDS with a fairly narrowband filter to eliminate any out of band spurious. You also might want to look at phase noise requirements, just in case.

Another possibility is to re-design the loop filter to be narrower. If you take it to 500 Hz, then that should help eliminate the reference spurious, and you could take it even narrower depending on lock time requirements.

When you were using a function generator as a reference source, you were adding a significant amount of noise to the signal, as a function generator phase noise is many dB higher than a reference oscillator, so no surprise there.

Answer 4

I think what we'll end up going with is a hybrid PLL/DDS setup. Ie, use the PLL in an integer-N mode to set the coarse frequency, and then mix onto that a fine-tunable signal from the DDS.

I've played around with adjusting the reference input frequency to the ADF4350 PLL board (using an SRS function generator), and while that does achieve what I was looking for, the FFT spectrum looks decidedly less happy as I adjust away from 10 MHz (or 20 MHz)...the central peak shifts as expected, but the noise floor jumps up from where it was at a 10 MHz reference frequency. I don't know nearly enough to say why this is, but using a DDS/PLL mixing scheme will get the small channel spacing I need in that high frequency range. Plus, it opens up the ability to do more complicated things like frequency sweeps, etc.