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The Xilinx Vivado's set_max_delay requires -from to be set.

Basically I'd like to set max delay TO a register. Because there can be lots of registers source to my destination register, I don't know their name.

  • set_max_delay 3 -datapath_only -to [get_cells dest_reg*] isn't valid because it doesn't have -from option.

My plan

  • Get all the input pins (D, CE, R) of the destination register

    • set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == "D" || REF_PIN_NAME == "CE" || REF_PIN_NAME == "R"}]
    • The danger is that there might be other input pins...
  • Get all the nets connected to these input pins

    • set nets [get_nets -segments -of_objects $dest_pins]
  • Track down all the output pins connected to these nets

    • set source_pins [get_pins -of_objects $nets -filter {IS_LEAF && DIRECTION == "OUT"}]
  • Get all the registers of these pins

    • set source [get_cells -of_objects $source_pins]

This looks too overkill just to add a CDC constraint on a single register.

Question

  • What's the best way of adding a constraint using only its name and nothing else?
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  • \$\begingroup\$ Did you try -from [get_cells *] and -from [get_ports in[*]] to include all input ports and registers sourcing your destination register? \$\endgroup\$ – Mitu Raj Apr 7 at 7:59
  • \$\begingroup\$ I believe that has a more or less big impact on the processing time. I tend to avoid wildcard. \$\endgroup\$ – Alexis Apr 7 at 14:01
  • \$\begingroup\$ Not sure if your claim about "processing time about wildcards" is true cz I never came across that. This is what people do normally. Nobody writes 10000 SDC lines for 10000 signals that fan into a register. Even if you do, the amount of effort synthesiser has to put is the same as you put a wildcard. Cz the no. of constraints to be solved by the Synthesiser in both cases is the same = 10000. \$\endgroup\$ – Mitu Raj Apr 7 at 14:07
  • \$\begingroup\$ I believe that has something to do with the database, wildcard queries are always heavier. Wildcard is O(n) while the way I do it should be maximum O(log n). Your answer is still valid to add quickly the constraint and it works! Thanks! \$\endgroup\$ – Alexis Apr 7 at 23:16
  • \$\begingroup\$ I shall put it as an answer then. \$\endgroup\$ – Mitu Raj Apr 8 at 3:43
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If dest_reg is the full hierarchial name of the destination register, then you can add two constraints to your SDC:

To constraint ALL paths from different input ports to your destination register:

set_max_delay -from [get_ports in [*]] -to [get_cells dest_reg] <delay>

To constraint ALL paths from different registers to your destination register:

set_max_delay -from [get_cells [*]] -to [get_cells dest_reg] <delay>

EDIT:

As in Vivado the above second command generates warnings as the wildcard generates unsupported paths as well, so registers have to be explicitly mentioned for get_cells . In Altera, get_registers can be used, in Vivado it is not supported, so a work around is needed for get_cells. Since registers follow the naming convention _reg in the netlist :

set_max_delay -from [get_cells *_reg*] -to [get_cells dest_reg] <delay>
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  • \$\begingroup\$ Actually I just tested and I get thousands of warnings listing all the cells (not only regs) possible in my design is not a valid startpoint. get_cells * is not appropriate. Also -hierarchical is necessary. \$\endgroup\$ – Alexis Apr 8 at 4:06
  • \$\begingroup\$ What is the warning message? \$\endgroup\$ – Mitu Raj Apr 8 at 4:07
  • \$\begingroup\$ [Constraints 18-402] set_max_delay: '*' is not a valid startpoint. ["/home/alexis/git/constraints.tcl":10] can be instances, LUTs, FFs ... \$\endgroup\$ – Alexis Apr 8 at 4:09
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    \$\begingroup\$ Regs have _reg in the name. \$\endgroup\$ – Alexis Apr 8 at 4:23
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    \$\begingroup\$ get_cells -hierarchy *_reg* works. You're selecting pins (C and D), that's wrong. Sometimes the compiler uses CE and/or R pins, not covered by your command. \$\endgroup\$ – Alexis Apr 8 at 9:39

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