How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)

Question

The Xilinx Vivado's set_max_delay requires -from to be set.

Basically I'd like to set max delay TO a register. Because there can be lots of registers source to my destination register, I don't know their name.

• set_max_delay 3 -datapath_only -to [get_cells dest_reg*] isn't valid because it doesn't have -from option.

My plan

• Get all the input pins (D, CE, R) of the destination register

  • set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == "D" || REF_PIN_NAME == "CE" || REF_PIN_NAME == "R"}]
  • The danger is that there might be other input pins...

• Get all the nets connected to these input pins

  • set nets [get_nets -segments -of_objects $dest_pins]

• Track down all the output pins connected to these nets

  • set source_pins [get_pins -of_objects $nets -filter {IS_LEAF && DIRECTION == "OUT"}]

• Get all the registers of these pins

  • set source [get_cells -of_objects $source_pins]

This looks too overkill just to add a CDC constraint on a single register.

Question

• What's the best way of adding a constraint using only its name and nothing else?

Answer 1

If dest_reg is the full hierarchial name of the destination register, then you can add two constraints to your SDC:

To constraint ALL paths from different input ports to your destination register:

set_max_delay -from [get_ports in [*]] -to [get_cells dest_reg] <delay>

To constraint ALL paths from different registers to your destination register:

set_max_delay -from [get_cells [*]] -to [get_cells dest_reg] <delay>

EDIT:

As in Vivado the above second command generates warnings as the wildcard generates unsupported paths as well, so registers have to be explicitly mentioned for get_cells . In Altera, get_registers can be used, in Vivado it is not supported, so a work around is needed for get_cells. Since registers follow the naming convention _reg in the netlist :

set_max_delay -from [get_cells *_reg*] -to [get_cells dest_reg] <delay>