# How do i solve a circuit when a capacitor is between in op amp inputs?

I am quite confused with this circuit. Most circuits I have seen don't have a capacitor between the op amp inputs. I tried to write out the differential equations using nodes, but I can't find enough equations to solve the system.

*The circuit showed in the picture is used for humidity measurement by measurement capacitance $$\C_x\$$, it is an old design but it still works for a range of humidity, i dont have the values of $$\C_s\$$ and $$\C_x\$$,but it seems that $$\C_x\$$ can range from $$\0-20pF\$$

My goal is understand how this circuit works, and find the mathematical relation between the output volatage of the op amp and $$\C_x\$$ , frequency and duty cycle of $$\S_1\$$, then calculate the values of each component in such a way that this relation more or less linear.

I didn't consider that the voltage between the inputs is zero, because I think capacitor $$\C_9\$$ takes time to be charged or the op amp takes time to make it zero. Do we have to always consider that the voltage between op amp inputs is zero?

Could someone suggest some steps to calculate the components of the circuit?, maybe I shoud remove $$\C_9\$$ at the beginning, calculate the component's values , and implement the circuit and then check which value of $$\C_9\$$ give a better performance.

• Where did you get the circuit? Were there any values assigned to the components? Commented Apr 7, 2021 at 15:27
• Assuming the opamp has proper feedback (does it?), what can we then say about the voltage between the inputs of the opamp? Commented Apr 7, 2021 at 15:34
• Does this answer your question? Purpose of a capacitor between op amp inputs in buffer circuit Commented Apr 7, 2021 at 15:48
• RF has no gain for feedback but some input attenuation to prevent nonlinear effects. AM demodulation... Commented Apr 7, 2021 at 16:21
• @arlen - Re: updated circuit: Are those switches alternating being closed? Commented Apr 9, 2021 at 13:05

You'll have to assume a finite gain for the op-amp (meaning the voltage between the inputs is small, but not zero), and preferably also a non-zero impedance for the reference diode to get a sensible answer.

The main reason for using this configuration is to prevent small DC shifts due to EMI, especially with a bipolar input op-amp, which should be a hint that a linear approximation is insufficient to fully analyze it.

General approach for analysis:

If Z3 and Z2 are primarily capacitive and Z1 primarily resistive at frequencies of interest, it all comes out as a 2nd order response, and Z2 can give some control of Q for instance. Op amp Zo could go alongside Z3 also, to refine the picture.

Update - with the rest of the OP circuit shown, some kind of ratiometric switched cap sensor, there is more going on...

• Have you verified or simulated that this is accurate? What do you suggest how C9,C6 affect the result for any choices? Commented Apr 9, 2021 at 12:26
• @Tony Stewart - The Aol expression, yes. The C (or series RC) across the op amp inputs, is just on paper for me. My impression was there are easier and more flexible ways to make a filter, and the terms containing GBW would make it imprecise. I thought the concept was more of a compensation thing to reduce peaking in unusual cases. But looking at the updated circuit from OP there seems to be more going on.... Commented Apr 9, 2021 at 12:48
• And from my analysis and simulation the non-inverting side does not attenuate noise., thus useless except lowering DC Zo for very low frequencies from 5 to 20 Ohms ( @ tbd If) yet very much current limited. So a 51 Ohm RC filter does a better job. The same is true for microwave. Commented Apr 9, 2021 at 14:41

There is no value of caps across Op Amp that will improve the result.

This is a common yet useless design.

The non-inverting Op Amp gain is Av+=1+|Av-| so the 1+ passes thru all the noise using the non-inverting input (unlike an LDO)

As a couple of reviewers did not appreciate my 1st answer that concludes nothing much can improve the noise (unless it was step load on OA) .

After the effects of integration and differentiation, and high input impedance and shunting the differential input voltage and thus feedback error correction...that the initial design does NOTHING to improve Vdd ripple.

However, as I previously concluded for an "Op Amp type only" SS load, and output RC filter will do more to attenuate Vdd ripple.

Proof by simulation with Op's question and output RC filter by comparison to Vdd pp simulated ripple to output ratio for dB of attenuation at f noise triangle.

Noticed I raised C9 from 1uF to 47uF because I was using 2.5kHz ripple to allow Op Amp to filter with gain error feedback (but doesn't work since gain is 1+ passes noise thru). If your noise is 100kHz SMPS, then 1uF is equivalent.

• Thank very much Tony , it helped me better understand this circuit Commented Apr 12, 2021 at 20:52

RF has no gain for feedback but some input attenuation to prevent nonlinear effects. AM demodulation...

But there is a integration factor for gain, so it is gradual HF rejection. So here the intent was Zener white noise attenuation but it also differentiates PSRR of the Vcc with Cf to a flat or no attenuation (C9/C6) of zener voltage error, rather than 1e5 min of DC error feedback from Op Amp load regulated error, so low frequency noise is worse if there is any load regulated noise ripple on Vcc. Otherwise not. Using an LM 384 on Falstad’s simulator, C9 across the input had only minor improvement only on OA output dynamic load current noise. It did not did not attenuate supply noise up to 1MHz as much as the Zener knee resistance @ 5mA which was 1% of supply noise.

Although this Cin assists as I originally noted to suppress RF demodulation, I have never considered or used it in this manner and I see now benefit other than very little x mV noise rejection on a simulated +/- t 5 mA Op Amp load regulated noise. Thus I conclude there is no benefit. If there is a significant dynamic load on Op Amp or a significantly low Analog noise requirement <5 mV the secondary LPF and/or buffer would be used.

## Bottom Line

The Zener is not very accurate compared to Bandgaps and the LDO’s would make a better Vcc/2 regulator. Yet if you have a spare OA and need just < low DC only current, this works without any caps with 100:1 attenuation of Vdd ripple.

This design has no benefit to me. Others may find ways to improve it. I tried. But C9 across input has no advantage except minimal attenuation of Load regulated noise added to output which is terrible on pulse noise due to GBW limits. (See Simulation and drag Gen. onto output) try changing any variable f ,C Noise and see the input impedance and output Vpp noise & traces.

I might only consider using Cin across diff inputs if input was on a long wire with RF and that can suppress AM radio audio being demodulated and amplified in a high gain preamp. But there are other ways to do that too. (Ferrite beads or LPF).

Also the input R’s ought to be matched or considered for Iio * R mismatch causing input voltage offset at high gain, here not critical considering Zener tolerances.

Sorry if I lost you after the 1st paragraph. You will understand with more experience.

• Tony, I was wondering if the concept of virtual short applies to OP's circuit. For V- = V+ it requires a negative feedback configuration, but it is not clear to me if that is the case, since both op-amp terminals are connected via C9. What do you think?
– Carl
Commented Apr 8, 2021 at 10:30
• Good question @Carl Both inputs are high Z and a small cap is also high Z except when Xc(f) < ZIn(diff) which for some values makes it worse by attenuating the difference between Mean input and desired mean output , with this low Z Vin+ (5 Ohms) I see no advantage to C9 but yes it is still a virtual ground but with output step load disturbances ( see my sim) is no longer an actual zero input but just an error junction and significant spikes on output. With 5mA step loads. Commented Apr 8, 2021 at 23:18
• So yes treat as virtual zero, but actual zero depends onDisturbances to load, GBW . But any good designer will buffer an Op Amp an output impedance <<1% of load at maximum slew rate such as using an LDO Commented Apr 8, 2021 at 23:21
• But if just powering an Op Amp which is pretty stable and Benign, no caps are needed at all !!! Commented Apr 8, 2021 at 23:22
• Thanks for the answer Tony. I think I need a lot more experience to understand your entire response.
– Carl
Commented Apr 9, 2021 at 9:54