I have a question about the secondary protection schemes for ESD for the I/O inside integrated circuits.

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I understand the purpose of the two clamping diodes closest to the I/O pad.

Q1: Why is there a resistor R_ESD and then another two clamping diodes closer to the inverter? I understand that the two additional diodes are for secondary clamping closer to the inverter but what is the purpose of R_ESD?

Q2: About ESD strikes in general - I see in several places, they talk about a strike being 1000 V and also a certain amperage. Why do they sometimes specify a certain current, won't that be dictated by the resistance that the strike voltage sees?

  • \$\begingroup\$ Your second question partly answers why there is a resistance in your question. You don't want those diodes to pass too much current and fry. \$\endgroup\$
    – DKNguyen
    Apr 7, 2021 at 22:30
  • \$\begingroup\$ Ah. So the resistance that the voltage strike sees will dictate the current. Without R_ESD + Second Set of Diodes, all the current would flow through the first diode since a diode presents a small resistance (forward-biased) and the voltage at the input to the gates would rise and possibly break the transistors. The R_ESD (I assume is chosen somewhat close to the diode on-resistance) takes some of this current and routes it to the second set of diodes and dumps to VDD. Now both of our diodes take a smaller amount of current and the voltage drop across R_ESD means our FETs aren't damaged. \$\endgroup\$ Apr 7, 2021 at 23:09
  • \$\begingroup\$ Is that somewhat correct (I hope :D)? My intuition for circuits isn't great :( \$\endgroup\$ Apr 7, 2021 at 23:10
  • 1
    \$\begingroup\$ Yes. Without a resistor, the diodes dissipate all the energy themselves and could fry. A resistor is much more suited to dissipating heat and it limits the current being injected into the diodes as well as into the power rails (you don't want the current being injected to be so large it disrupts the power rail). To be fair, R1 and R2 seem a bit redundant to me as well. \$\endgroup\$
    – DKNguyen
    Apr 7, 2021 at 23:16
  • \$\begingroup\$ @DKNguyen Thank you! \$\endgroup\$ Apr 8, 2021 at 1:19

1 Answer 1


Regarding the second question - each actual ESD strike is random. In order to make it easier to test, there are standards that specify certain conditions eg HBM (human body model).

Since an ESD event is a discharge, there’s a very fast change of voltage and current, so the actual current that flows is rather complex due to inductance, capacitance and resistance. There’s also flashover that affects the actual behaviour. The challenge of solving ESD problems is understanding where it comes into your circuit, where it leaves and what happens in between. In many cases resistors cease to exist electrically as the arc flashes over them.

  • \$\begingroup\$ I see. Very interesting, I just had a look at some of the models, I see what you mean now, there are caps with certain charged voltages and inductors, so the peak current is defined by those. More complex than I thought! Thank you \$\endgroup\$ Apr 8, 2021 at 1:19

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