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I am trying to simulate a half bridge for a 3 phase motor driver. enter image description here

When my high side FET transitions off, during the dead time, the switch node voltage is 25V. I would expect this voltage to be a diode drop below ground as the body diode of the low side FET should supply the current to the inductive load in the following loop:

enter image description here

When the low side fet transitions on, the sudden dv/dt caused by the switch node transitioning from ~25V to ~0V appears to couple to the high side FET gate through Cgs and cause a large negative transient.

enter image description here

I'm trying to understand why the switch node is staying at 25V after the high side FET turns off, and how to resolve the dv/dt that is causing my high side FET gate transient.

Currently I suspect my low side FET snubber cap is holding up the switch node at 25V, but not sure how to fix the negative voltage transient at the high side gate.

Edit: Updated my circuit after fixing the items pointed out in the comments, still getting large negative transients on my low side gate

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I've tried slowing down the turn-on of the high side FET, making the snubber cap on the low side larger.

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    \$\begingroup\$ Look up high-side gate driver. You have a source follower even if you are driving with 60V. That high gate voltage is part of the problem. That gate current is making a huge detour through your entire circuit instead of just around the gate-source loop that it needs. \$\endgroup\$ – DKNguyen Apr 8 at 4:30
  • \$\begingroup\$ Is there any reason why you would not be driving M1 with V1 referenced to the sw_node? \$\endgroup\$ – a concerned citizen Apr 8 at 7:10
  • \$\begingroup\$ Updated my mistake of not driving the high side with respect to source. The issues improved significantly, however I'm a little stumped on the massive negative transients I'm seeing on my low side gate now (posted above). \$\endgroup\$ – user2828776 Apr 9 at 5:52
  • \$\begingroup\$ Try removing the snubbers across the MOSFETs and putting just one snubber across the inductive load itself. There is no direct snubbing of the thing that needs snubbing the most. Snubbers across the MOSFETs decreases the dV/dT across them but as far as L8 is concerned its flyback current has to go all through the supply so it isn't getting snubbed directly. I also think you need to add more parasitic inductors (not inductance) if you are trying to account for that since you have inconsistent bypassing of the parasitic inductors you do have around the source and drain of the MOSFETs. \$\endgroup\$ – DKNguyen Apr 9 at 5:52
  • \$\begingroup\$ And what is D3 supposed to be for? \$\endgroup\$ – DKNguyen Apr 9 at 6:02

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