# Where does the additional capacitance come from ? (Pull-up delay)

I am using a couple of daisy-chained ADG1414 switches, that use a serial input of the switch state.

Data is clocked into the first chip in the chain into an SDI pin, and clocked out via an open-drain SDO pin to the subsequent chips.

I am pulling up the SDO with a 680 Ohm resistor to 3.3 V. The datasheet specifies 4 pF of Open-Drain Capacitance and 4 pF of SDI input capacitance.

I thus estimate a conservative time constant of 10 pF * 680 Ohm = 6.8 ns.

In practise, I measure a time constant of ~18 ns on the board, implying a node capacitance on the order of 26 pF. This slows down my serial input by a factor of 2 to 3. Of course I could use smaller pull-ups but I would prefer not to.

Where is that additional ~18 pF of parasitic capacitance located ? The screenshot shows an example SDI-to-SDO connection. The trace is 0.254 mm wide and ~9 mm long. There is no GND plane under the trace; the next plane is 1.6 mm away. The chip on the right is the SDO side.

One guess would be of course the stray capacitance to the neighboring conductors. I crudely estimated this as a plate capacitor with d =0.254 mm and A = 35µm * 9 mm. The result is way sub-pF. This sounds too low, so I wonder what better way there is to estimate this stray capacitance.