I am using a couple of daisy-chained ADG1414 switches, that use a serial input of the switch state.

Data is clocked into the first chip in the chain into an SDI pin, and clocked out via an open-drain SDO pin to the subsequent chips.

I am pulling up the SDO with a 680 Ohm resistor to 3.3 V. The datasheet specifies 4 pF of Open-Drain Capacitance and 4 pF of SDI input capacitance.

I thus estimate a conservative time constant of 10 pF * 680 Ohm = 6.8 ns.

In practise, I measure a time constant of ~18 ns on the board, implying a node capacitance on the order of 26 pF. This slows down my serial input by a factor of 2 to 3. Of course I could use smaller pull-ups but I would prefer not to.

Where is that additional ~18 pF of parasitic capacitance located ? The screenshot shows an example SDI-to-SDO connection. The trace is 0.254 mm wide and ~9 mm long. There is no GND plane under the trace; the next plane is 1.6 mm away. The chip on the right is the SDO side.

enter image description here

One guess would be of course the stray capacitance to the neighboring conductors. I crudely estimated this as a plate capacitor with d =0.254 mm and A = 35µm * 9 mm. The result is way sub-pF. This sounds too low, so I wonder what better way there is to estimate this stray capacitance.


1 Answer 1


How are you measuring the rise time?

Don't forget the capacitance of the scope probe which is in the ballpark of 18pF (My Siglent probe is 18-22pF in 10:1 mode and 85-120pF in 1:1).

  • \$\begingroup\$ I do use the scope with 10:1 probe, but I suppose it is well compensated, as I can resolve the much faster fall-time to be about 3-4 ns and dont get overshoot. \$\endgroup\$
    – tobalt
    Commented Apr 8, 2021 at 14:55
  • \$\begingroup\$ Ahh now I see. You mean that the scope cable has this capacitance.. OMG of course.. :) Thanks, that would mean that everything actually works as planned :) \$\endgroup\$
    – tobalt
    Commented Apr 8, 2021 at 14:56

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