I have a falling edge detector built based on a D flip-flop as shown in the following figure:


Components: 74hc74, 74ls04n, 74hc08

A sample output is shown below (I invert the output since I need it as an active low):

logic analyzer output

My question is why it sometimes doesn't detect the falling edge?

Thank you all so much!

The problem was the logic analyzer sampling rate and frequency as @Elliot Alderson mentioned.

I re-configured the PulseView and finally could capture the output correctly (indeed there was nothing wrong with the circuit itself)

logic analyzer output

  • 2
    \$\begingroup\$ How did you get the output waveforms? Is this a simulation or a real circuit? If a real circuit, how did you capture the signals? \$\endgroup\$ Commented Apr 8, 2021 at 16:29
  • 2
    \$\begingroup\$ This circuit is twitchy and is relying on propogation delays... \$\endgroup\$
    – user16222
    Commented Apr 8, 2021 at 16:49
  • 1
    \$\begingroup\$ Thank you all for your comments. @ElliotAlderson This is a real circuit and I captured the output with a logic analyzer. \$\endgroup\$
    – Sina
    Commented Apr 8, 2021 at 18:06
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    \$\begingroup\$ This is just block diagram you have shown. We never know if this is what you ACTUALLY wired and built on hardware. \$\endgroup\$
    – Mitu Raj
    Commented Apr 8, 2021 at 18:22
  • 1
    \$\begingroup\$ Would you need a synch flip flop chain preceding this like you would in an FPGA to handle metastability? \$\endgroup\$
    – DKNguyen
    Commented Apr 8, 2021 at 19:50

1 Answer 1


My guess is that the pulses are too short for the logic analyzer to catch them. Logic analyzers sample the signals at a constant rate, and if the time between samples is longer than your pulse width then the logic analyzer simply won't see it.

Try decreasing the sampling time significantly, or switch to an oscilloscope.


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