I have a design that is erroring at compilation time with (among other errors) a bunch of duplicate net name errors. I have searched around including reading up on the top result for this problem (changing the net identifier scope doesn't solve the issue and causes many more errors).
The error makes no sense in context. I have three power rails in this design (12V 5V and 3V3). The project is setup in a hierarchy (top level showing connections between all other sheets). Power from the power supply to loads is done using Ports. Each schematic uses Net Labels internally to connect the Input Port to various components.
The error occurs on all schematics that use Net Labels which I guess makes sense but the nets are supposed to have the same name since they are connected (but visually it would be messy to draw a wire between the two points).
How do I inform Altium that the duplicates are intended?
P.S. I apologize for what may be terrible grammer it is currently 2:23AM as I write this.