2
\$\begingroup\$

I'd like to simulate the digital 74LVTxx chips with their analog characteristics. Packages like Multisim and OrCad only have the basic models (e.g. 74LS04N).

============= SPICE Model =================
.MODEL 74LSIC04 d_chip ( behaviour= "
+; 74LSIC04 Hex Inverter
+/inputs 1A 2A 3A 4A 5A 6A
+/outputs 1Y 2Y 3Y 4Y 5Y 6Y
+/module INV08
+/inputs A
+/outputs Y
+/table 2
+; A  Y
+  L  H
+  H  L
+/delay 1
+; input output Rise time Fall time
+   A          Y      15n         15n
+/endmodule
+/instance INV08 1A 1Y
+/instance INV08 2A 2Y
+/instance INV08 3A 3Y
+/instance INV08 4A 4Y
+/instance INV08 5A 5Y
+/instance INV08 6A 6Y
+")
============= Model template =================
a%p [%t1A?%t:d%t;1A
+      %t2A?%t:d%t;2A
...
+      %tVCC?%t:d%t;VCC
+      %tGND?%t:d%t;GND] %m

I went to NXP and downloaded the circa 1999 PSpice file holding a family of 74LVP models called lvtps.cir. Trying to import this into Multisim resulted in an unconnected spaghetti network. Editing a similar part with this *.cir in the DB editor led to many, many errors. OrCad has no idea what to do with it. Only Cadence PSpice could "simulate" the lvtps.cir file, but that doesn't help me add a 74LVTxx chip to a schematic.

LVT PSPICE MODELS
**************************************************************************
* LVTPS.CIR
* Low Voltage BiCMOS Logic
* Logic Products Group
* Philips Semiconductors
* 3/9/99
* Version 1.02
* Revision Comment: Subcircuits added for expansion of available LVT 
* device simulations.
...
**************************************************************
* PACKAGE MODELS
.LIB "lvtpkps.s"

* SUBCIRCUIT MODELS
.LIB "subps.lib"

**************************************************************
* UNCOMMENT ONLY THE DEVICE MODEL FILE DESIRED
* NOMINAL, SLOW, AND FAST FAB PROCESS CORNERS

* NOMINAL PARAMETERS
  .LIB "nomps.lib"
...

Question: How to simulate these 74LVTxx models?* Does this cir file need to be flattened by hand?

enter image description here

*Not asking for a software recommendation as I have a few.

\$\endgroup\$
4
  • \$\begingroup\$ None looks like SPICE syntax, and the first might resemble LTspice's state machine, if you squint enough. You need SPICE models, that have valid SPICE .subckt or .model. The .model you see there is not one recognizable by SPICE, but it might be by some exotic flavour of it (i.e. custom made). \$\endgroup\$ Apr 9 at 19:14
  • \$\begingroup\$ I've used the Nexperia logic family models to create my own libraries. I had to do this for each part I needed, so I would say the answer to your 2nd question is "Yes". Are there specific part#'s you need for your application or are you in search for off-the-shelf models for every part in the family? \$\endgroup\$
    – Ste Kulov
    Apr 9 at 21:40
  • \$\begingroup\$ @SteKulov The 74LVT04 part would absolutely save the day. I didn't sleep last night. Pastebin? :) Do you have tips for the second part of my question? I tried copying subckt parts to the cir, but got lost when the external X parts didn't match anything (e.g. GSOINV --> XPK14_0 --> ??). \$\endgroup\$
    – Drakes
    Apr 9 at 21:50
  • \$\begingroup\$ @Drakes I gave it a shot. See the answer I posted. \$\endgroup\$
    – Ste Kulov
    Apr 10 at 5:29
3
\$\begingroup\$

I have previously only massaged Philips/NXP/Nexperia logic models from the HCT and LVC families, but took a stab at the LVT since you specifically requested the 74LVT04 in the question comments. It's a little more complicated than the other two, so I might have screwed something up in the process. With that disclaimer...below is the 74LVT04.lib file which simulates a single gate when calling a single instance of 74LVT04. If a 74LVT1G04 existed it would be more equivalent to that (see 74LVC1G04 to see what I'm talking about). The "nominal parameters" from nomps.lib were used. Also note that the package parasitics from lvtpkps.s are not present here.

* LVT Logic Family Single Buffered Inverter using nominal parameters
*********************************************************************
.SUBCKT 74LVT04 IN OUT VCC GND
R8 VCC 128 1K  
R7 VCC 129 1K    
M5 128 130 GND GND HVNMOS  L=800E-9 W=4E-6 NRD= 6.625E-02 NRS= 6.625E-02 AD=7.2E-12 AS=7.2E-12
+  PD=11.6E-6 PS=11.6E-6   
M4 129 131 GND GND HVNMOS  L=800E-9 W=4E-6 NRD= 6.625E-02 NRS= 6.625E-02 AD=7.2E-12 AS=7.2E-12
+  PD=11.6E-6 PS=11.6E-6   
X0 130 133 OUT VCC GND OUTBUFH  
X1 131 IN 133 VCC GND INBUFBIG    
.ENDS 74LVT04
*********************************************************************
*********************************************************************
.MODEL HVNMOS NMOS
+ LEVEL=3 TOX=15E-9 UO=460 VTO=0.7 NFS=1E11 NSUB=1E17
+ VMAX=153.4K XJ=0.2884E-6
+ RSH=6.0E3
+ DELTA=0.598 THETA=0.04 ETA=0.0649 KAPPA=20E-18
+ CJ=0.461E-3 MJ=0.325 CJSW=0.274E-9 MJSW=0.249 PB=0.76
+ CGDO=0.475E-9 CGSO=0.475E-9
+ JS=420E-9 IS=0
+ WD=0.129E-6  KF=3.180E-27  AF=1.160
.MODEL HVPMOS PMOS
+ LEVEL=3 TOX=15E-9 UO=180 VTO=-0.7 NFS=1E12 NSUB=7E16
+ VMAX=172K XJ=0.254E-6
+ RSH=4.0E3 
+ DELTA=2 THETA=0.12 ETA=0.0805 KAPPA=20E-18
+ CJ=0.354E-3 MJ=0.328 CJSW=0.226E-9 MJSW=0.27 PB=0.65
+ CGDO=0.38E-9 CGSO=0.38E-9
+ JS=120E-9 IS=0
+ WD=0.11E-6  KF=4.180E-28  AF=1.160
*********************************************************************
*********************************************************************
.SUBCKT OUTBUFH 107 108 109 VCC GND
XQQ136 110 111 109  GND  HV38STSBDETCNW  
XQQ190 112 112 113  GND  HV3STDBTC  
XQQ191 114 112 115  GND  HV3STDBTC  
XQQ189 107 116  GND   GND  HV3STDBTC  
XD135 VCC 110  GND  HVDS2X45P2  
XD140 115 VCC  GND  HVDS2X3  
XD182 109 117  GND  HVDS3X8  
XD183 VCC 118  GND  HVDS3X8  
XD184 VCC 117  GND  HVDS3X8  
XD185 119 107  GND  HVDS3X5  
XD186 VCC 110  GND  HVDS2X45P2  
XD187 113 109  GND  HVDS3X8  
Q178 115 120  GND   GND  HV3DBTC  
Q180 109 115  GND   GND  HV38SBDETCNW  
Q179 118 121 107  GND  HV3DBTC  
M165 122 108 VCC VCC HVPMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=18E-12 AS=18E-12 PD=23.6E-6
+  PS=23.6E-6   
M164 123 122 VCC VCC HVPMOS  L=800E-9 W=24E-6 NRD= 1.104E-02 NRS= 1.104E-02 AD=43.2E-12 AS=43.2E-12
+  PD=27.6E-6 PS=27.6E-6   
M163 121 108 VCC VCC HVPMOS  L=800E-9 W=35E-6 NRD= 7.571E-03 NRS= 7.571E-03 AD=63E-12 AS=63E-12 PD=73.6E-6
+  PS=73.6E-6   
M166 112 108 123 VCC HVPMOS  L=800E-9 W=24E-6 NRD= 1.104E-02 NRS= 1.104E-02 AD=43.2E-12 AS=43.2E-12
+  PD=51.6E-6 PS=51.6E-6   
R162 108 111 500.0  
R160 VCC 114 600.0  
R161 VCC 123 8E3  
M137 109 VCC 119 117 HVPMOS  L=1E-6 W=20E-6 NRD= 1.325E-02 NRS= 1.325E-02 AD=3.6E-12 AS=3.6E-12 PD=7.6E-6
+  PS=7.6E-6   
M162 107 108 118 118 HVPMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=18E-12 AS=18E-12 PD=23.6E-6
+  PS=23.6E-6   
M138 109 107 VCC 117 HVPMOS  L=1E-6 W=650E-6 NRD= 4.077E-04 NRS= 4.077E-04 AD=1.17E-9 AS=1.17E-9 PD=103.6E-6
+  PS=103.6E-6   
M136 119 VCC 107 117 HVPMOS  L=1E-6 W=2E-6 NRD= 1.325E-01 NRS= 1.325E-01 AD=3.6E-12 AS=3.6E-12 PD=7.6E-6
+  PS=7.6E-6   
X134 124 125 VCC GND OUTBUFH_1   
X135 107 124 VCC GND OUTBUFH_2   
M177 112 108  GND   GND  HVNMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=3.6E-12 AS=3.6E-12
+  PD=7.6E-6 PS=7.6E-6   
M176 115 108  GND   GND  HVNMOS  L=800E-9 W=30E-6 NRD= 8.833E-03 NRS= 8.833E-03 AD=3.6E-12 AS=3.6E-12
+  PD=7.6E-6 PS=7.6E-6   
M175 122 108  GND   GND  HVNMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=18E-12 AS=18E-12
+  PD=23.6E-6 PS=23.6E-6   
M167 107 108  GND   GND  HVNMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=18E-12 AS=18E-12
+  PD=23.6E-6 PS=23.6E-6   
M168  GND  VCC 116  GND  HVNMOS  L=800E-9 W=4E-6 NRD= 6.625E-02 NRS= 6.625E-02 AD=7.2E-12 AS=7.2E-12
+  PD=11.6E-6 PS=11.6E-6   
M169 116 125 108  GND  HVNMOS  L=800E-9 W=30E-6 NRD= 8.833E-03 NRS= 8.833E-03 AD=54E-12 AS=54E-12
+  PD=63.6E-6 PS=63.6E-6   
M170 111 122  GND   GND  HVNMOS  L=800E-9 W=20E-6 NRD= 1.325E-02 NRS= 1.325E-02 AD=36E-12 AS=36E-12
+  PD=43.6E-6 PS=43.6E-6   
M173 121 108  GND   GND  HVNMOS  L=800E-9 W=15E-6 NRD= 1.767E-02 NRS= 1.767E-02 AD=27E-12 AS=27E-12
+  PD=33.6E-6 PS=33.6E-6   
M171 120 108  GND   GND  HVNMOS  L=800E-9 W=2E-6 NRD= 1.325E-01 NRS= 1.325E-01 AD=3.6E-12 AS=3.6E-12
+  PD=7.6E-6 PS=7.6E-6   
M172 108 125 120  GND  HVNMOS  L=800E-9 W=10E-6 NRD= 2.650E-02 NRS= 2.650E-02 AD=18E-12 AS=18E-12
+  PD=23.6E-6 PS=23.6E-6   
M174 109 122  GND   GND  HVNMOS  L=1E-6 W=30E-6 NRD= 8.833E-03 NRS= 8.833E-03 AD=54E-12 AS=54E-12
+  PD=63.6E-6 PS=63.6E-6   
.ENDS OUTBUFH
.SUBCKT OUTBUFH_2 126 127 VCC GND
MQN7 127 126  GND   GND  HVNMOS  L=8E-7 W=6E-06 NRD= 4.417E-02 NRS= 4.417E-02 AD=36E-12 AS=36E-12
+  PD=43.6E-6 PS=43.6E-6   
MQP8 127 126 VCC VCC HVPMOS  L=8E-7 W=4E-06 NRD= 6.625E-02 NRS= 6.625E-02 AD=36E-12 AS=36E-12 PD=43.6E-6
+  PS=43.6E-6   
.ENDS OUTBUFH_2  
.SUBCKT OUTBUFH_1 126 127 VCC GND 
MQN7 127 126  GND   GND  HVNMOS  L=8E-7 W=1E-05 NRD= 2.650E-02 NRS= 2.650E-02 AD=36E-12 AS=36E-12
+  PD=43.6E-6 PS=43.6E-6   
MQP8 127 126 VCC VCC HVPMOS  L=8E-7 W=1E-05 NRD= 2.650E-02 NRS= 2.650E-02 AD=36E-12 AS=36E-12 PD=43.6E-6
+  PS=43.6E-6   
.ENDS OUTBUFH_1
*********************************************************************
*********************************************************************
.SUBCKT INBUFBIG 107 108 109 VCC GND  
X7 108 109 VCC GND INBUFBIG_3   
X19 108 107 VCC GND INBUFBIG_4   
Q11 VCC 107 109  GND  HV3DBTC    
.ENDS INBUFBIG  
.SUBCKT INBUFBIG_3 126 127 VCC GND 
MQN7 127 126  GND   GND  HVNMOS  L=8E-7 W=4E-05 NRD= 6.625E-03 NRS= 6.625E-03 AD=36E-12 AS=36E-12
+  PD=43.6E-6 PS=43.6E-6   
MQP8 127 126 VCC VCC HVPMOS  L=8E-7 W=1E-05 NRD= 2.650E-02 NRS= 2.650E-02 AD=36E-12 AS=36E-12 PD=43.6E-6
+  PS=43.6E-6   
.ENDS INBUFBIG_3  
.SUBCKT INBUFBIG_4 126 127 VCC GND
MQN7 127 126  GND   GND  HVNMOS  L=8E-7 W=2E-5 NRD= 1.325E-02 NRS= 1.325E-02 AD=36E-12 AS=36E-12
+  PD=43.6E-6 PS=43.6E-6   
MQP8 127 126 VCC VCC HVPMOS  L=8E-7 W=4E-05 NRD= 6.625E-03 NRS= 6.625E-03 AD=36E-12 AS=36E-12 PD=43.6E-6
+  PS=43.6E-6   
.ENDS INBUFBIG_4
*********************************************************************
*********************************************************************
.SUBCKT  HV38STSBDETCNW  1 2 3 4
QN   1 2 3 4 MTRN
DSCH   2 1 SCH
.MODEL  MTRN  NPN  
+IS =     1.7195E-16   BF =     133.8       BR =     7.926E+00
+IKF =    0.06726      IKR =    0.01206     NF =     0.997
+NR =     0.9918       VAF =    30.0        VAR =    2.69
+RC =     1.477        RBM =    1.079       RB =     126
+IRB =    2.02E-5      RE =     0.294       CJE =    4.408E-13
+VJE =    0.91         MJE =    0.47        CJC =    2.709E-13
+VJC =    0.6          MJC =    0.28        XCJC =   1.000E+00
+FC =     8.750E-01    PTF =    1.000E+01   CJS =    2.585E-13
+VJS =    0.636        MJS =    0.36        TF =     11.0E-12
+TR =     8.573E-10    EG =     1.156
+ISE =    1.539E-16    ISC =    0.32E-14    XTB =    0.5266
+XTI =    3.687        XTF =    15          VTF =    1.5  
+ITF =    0.26         NC = 2.131           NE = 1.603
.MODEL SCH D (IS =    110.8E-15  N =      1.0367
+         RS =     58   CJO =    4.95E-14   VJ =     0.7   M =      0.6
+         EG =    0.8633  XTI =   1.001)
.ENDS HV38STSBDETCNW
.SUBCKT  HV3STDBTC  1 2 3 4
QN   1 2 3 4 MTRN
DSCH   2 1 SCH
.MODEL  MTRN  NPN  IS= 7.72E-18  BF= 1.25E+02  VAF= 2.20E+01  IKF= 3.46E-03
+  BR= 4.00E+00  VAR= 4.00E+00  IKR= 1.02E-01  RB= 8.39E+02  IRB= 6.00E-07
+  RBM= 8.33E+00  RE= 1.06E+01  RC= 3.84E+01  XTB= 5.00E-01  EG= 1.20E+00
+  XTI= 3.00E+00  CJE= 1.74E-14  VJE= 9.10E-01  MJE= 4.70E-01  TF= 8.50E-12
+  XTF= 1.80E+01  VTF= 2.50E+00  ITF= 1.60E-02  PTF= 1.00E+01
+  CJC= 1.09E-14  VJC= 6.00E-01  MJC= 2.80E-01  TR= 4.11E-10
+  ISE=0.0  ISC=0.0  NF= 1.00E+00  NR= 1.00E+00  CJS= 5.20E-14
+  VJS= 6.36E-01  MJS= 3.60E-01
.MODEL SCH D (IS= 4.17E-14  RS= 1.98E+02  N= 1.04E+00  CJO= 9.90E-15  VJ= 7.00E-01
+      M= 6.00E-01  EG= 7.60E-01  XTI= 3.00E+00)
.ENDS HV3STDBTC
.SUBCKT  HVDS2X45P2  1 2 3
DDIO 1 2 DIOM
DCAP 3 2 JCAPM 
.MODEL DIOM D IS= 4.30E-13  RS= 1.97E+01  N= 1.04E+00  CJO= 1.02E-13
+      VJ= 7.00E-01 M= 6.00E-01  EG= 7.60E-01  XTI= 3.00E+00
.MODEL JCAPM D CJO= 1.77E-13  VJ= 6.36E-01  M= 3.60E-01
.ENDS HVDS2X45P2
.SUBCKT  HVDS2X3  1 2 3
DDIO 1 2 DIOM
DCAP 3 2 JCAPM OFF
.MODEL DIOM D (IS= 2.73E-14  RS= 3.13E+02  N= 1.04E+00  CJO= 1.10E-14
+      VJ= 7.00E-01 M= 6.00E-01  EG= 7.60E-01  XTI= 3.00E+00)
.MODEL JCAPM D (CJO= 3.65E-14  VJ= 6.36E-01  M= 3.60E-01)
.ENDS HVDS2X3
.SUBCKT  HVDS3X8  1 2 3
DDIO 1 2 DIOM
DCAP 3 2 JCAPM OFF
.MODEL DIOM D (IS= 1.13E-13  RS= 8.40E+01  N= 1.04E+00  CJO= 3.80E-14
+      VJ= 7.00E-01 M= 6.00E-01  EG= 7.60E-01  XTI= 3.00E+00)
.MODEL JCAPM D (CJO= 5.77E-14  VJ= 6.36E-01  M= 3.60E-01)
.ENDS HVDS3X8
.SUBCKT  HVDS3X5  1 2 3
DDIO 1 2 DIOM
DCAP 3 2 JCAPM OFF
.MODEL DIOM D (IS= 7.03E-14  RS= 1.34E+02  N= 1.04E+00  CJO= 2.38E-14
+      VJ= 7.00E-01 M= 6.00E-01  EG= 7.60E-01  XTI= 3.00E+00)
.MODEL JCAPM D (CJO= 4.68E-14  VJ= 6.36E-01  M= 3.60E-01)
.ENDS HVDS3X5
.MODEL  HV3DBTC  NPN  IS= 7.72E-18  BF= 1.25E+02  VAF= 2.20E+01  IKF= 3.46E-03
+  BR= 4.00E+00  VAR= 4.00E+00  IKR= 1.02E-01  RB= 8.39E+02  IRB= 6.00E-07
+  RBM= 8.33E+00  RE= 1.06E+01  RC= 1.00E+02  XTB= 5.00E-01  EG= 1.20E+00
+  XTI= 3.00E+00  CJE= 1.74E-14  VJE= 9.10E-01  MJE= 4.70E-01  TF= 8.50E-12
+  XTF= 1.80E+01  VTF= 2.50E+00  ITF= 1.60E-02  PTF= 1.00E+01
+  CJC= 8.74E-15  VJC= 6.00E-01  MJC= 2.80E-01  TR= 3.32E-10
+  ISE=0.0  ISC=0.0  NF= 1.00E+00  NR= 1.00E+00  CJS= 3.89E-14
+  VJS= 6.36E-01  MJS= 3.60E-01
.MODEL  HV38SBDETCNW  NPN  
+IS =     1.72E-16   BF =     133.8      BR =    7.926E+00  
+IKF =    0.06726    IKR =    0.01206    NF =     0.9997   
+NR =     0.9918     VAF =    30.0       VAR =    2.69
+RC =     3.686
+RBM =    1.079      RB =     126    IRB =    2.02E-5 
+RE =     2.94E-01   CJE =    4.408E-13  
+VJE =    0.91       MJE =    0.47       CJC =    2.921E-13  
+VJC =    0.6        MJC =    0.28       XCJC =   1.000E+00
+FC =     8.750E-01  PTF =    1.000E+01  CJS =    2.585E-13
+VJS =    0.636      MJS =    0.36       TF =     11.0E-12
+TR =     8.573E-10  EG =     1.156
+ISE =    1.539E-16  ISC =    0.32E-14   XTB =    0.5266
+XTI =    3.687      XTF =    15         VTF =    1.5
+ITF =    0.26       nc = 2.131          ne = 1.603
*********************************************************************
*********************************************************************

You can also create a full chip 74LVT04D (SO14) by creating another subcircuit which calls 6 instances of the single gate subcircuit. Below is an example of this (untested). I didn't attempt it, but this is where you should manually add the package parasitics if you need that extra accuracy.

.SUBCKT 74LVT04D IN1 OUT1 IN2 OUT2 IN3 OUT3 GND OUT4 IN4 OUT5 IN5 OUT6 IN6 VCC
X1 IN1 OUT1 VCC GND 74LVT04
X2 IN2 OUT2 VCC GND 74LVT04
X3 IN3 OUT3 VCC GND 74LVT04
X4 IN4 OUT4 VCC GND 74LVT04
X5 IN5 OUT5 VCC GND 74LVT04
X6 IN6 OUT6 VCC GND 74LVT04
.ENDS 74LVT04D

I don't use PSpice because all the cool kidz (yes, with a Z) use LTspice. Therefore, below are some screenshots from LTspice which I took...while wearing my shades of course. I also included the code for the LTspice symbol (74LVT04.asy file) I used.

enter image description here

Version 4
SymbolType CELL
LINE Normal -32 -32 32 0
LINE Normal -32 32 32 0
LINE Normal -32 -32 -32 32
LINE Normal 0 -32 0 -16
LINE Normal 0 32 0 16
CIRCLE Normal 48 8 32 -8
WINDOW 0 24 -32 Left 2
WINDOW 3 24 32 Left 2
SYMATTR Value 74LVT04
SYMATTR Prefix X
SYMATTR Description LVT Family Inverting Buffer
SYMATTR ModelFile 74LVT04.lib
PIN -32 0 NONE 0
PINATTR PinName IN
PINATTR SpiceOrder 1
PIN 48 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 2
PIN 0 -32 NONE 0
PINATTR PinName VCC
PINATTR SpiceOrder 3
PIN 0 32 NONE 0
PINATTR PinName GND
PINATTR SpiceOrder 4
\$\endgroup\$
4
  • \$\begingroup\$ This works well, actually. The hex 74LVT04D didn't pan out because the model needed 17 pins, so I chained two of the 74LVT04 together. Wonderful. I could even simulate the ringing. Somehow the schematic led to MHz of ringing, and Vpp in the kV, but that is my problem. BTW, how did you know to convert $G_GND and $G_IGND and $G_VCC? \$\endgroup\$
    – Drakes
    Apr 11 at 3:59
  • 1
    \$\begingroup\$ @Drakes Nodes whose names start with $G_ are global nodes, and it just means they are the same whether inside a subcircuit or outside of it -- i.e. they can be accessed from outside their scope. Not using the notation reverts to the usual meaning of "what goes inside, stays inside [the subcircuits]". BTW, "thanks" or similar meaning words are replaced with the check mark beside the answer; optional upvote for what is considered a very good, or better, answer. \$\endgroup\$ Apr 11 at 7:42
  • \$\begingroup\$ @Drakes It wasn't straightforward to figure out. I also had to deduce that $G_100 was their internal VDD node. Anyway, I got rid of all the globals because I think it's always important to have the ability to "float" the subcircuit in case you need to put noise sources in line with GND (VSS) and/or VDD. It's more representative of a real world circuit too. Sorry, I made the entire chip subcircuit for 14 pins because that's what the Nexperia datasheet was saying. \$\endgroup\$
    – Ste Kulov
    Apr 11 at 16:25
  • \$\begingroup\$ ✓ You rock, friend. I was able to get your simulation up and running. \$\endgroup\$
    – Drakes
    Apr 11 at 16:51
0
\$\begingroup\$

74LVT chips are 3.6 V low Ron drivers with 7V output tolerance for bus driver uses only, not ‘04 gates. Correction

They rate these 3.3V chips at -10% or 3.0V using currents of 32 mA or pulse 64mA and provide the Vol, Voh. As these are nonlinear RdsOn’s sensitive to supply voltage, simulation must consider Vdd, and tolerance options of Nom or min or max.

Consider them as 10 Ohm drivers or confirm Vol/Iol at your leisure for your Vdd tolerance.

If you need an '04 gate in 3.6V logic use the standard 74ALVC04 for that matter all 74ALC' family which is like the AtMega ~ 25 Ohms nom @ 3.3V +/-50% but some have tighter tolerances or lower resistance such as Nexperia who are 12.5 Ohms nom at 3V so this value is easy to remember if you understand to read the datasheet and note it rises with lower Vdd voltage and higher temps ( lower Ron when coldest)

VCC = 3.0 V LOW-level output voltage
Io = 18 mA; Vol= 0.23 typ @ 25'C =0.4 V max at max T.
IO = 24 mA; Vol= 0.30 typ @ 25'C =0.55 V max at max T.
Computing Ron or Zol= 230mV/18mA=12.8 Ohms thus for the 2 conditions and 2 temperatures 25, 85'C
Zol [Ω]= 12.8, 12.5 nom @ 25'C and
Zol [Ω} = 16.7, 22.9 Max at 85'C

The other parameter to compare CMOS families and OEMs is the dynamic capacitance.

\$\endgroup\$
4
  • 1
    \$\begingroup\$ I think you are from an advanced future and have time-traveled back to the present to save us, and also took the time to write this answer. I appreciate that you think outside the box to use existing parts to achieve my goal. +1 \$\endgroup\$
    – Drakes
    Apr 11 at 16:55
  • 1
    \$\begingroup\$ I can recall PIN numbers for 4000 series CMOS from frequent experience mid 70’s but I can’t recall what I had for dinner last week. Repetition makes one look like a genius, which I am not but attention to details on impedance is simply “Ohm’s Law” \$\endgroup\$ Apr 11 at 16:57
  • \$\begingroup\$ LVT04P has VCC = 3.0 V; IOH = -20 mA Voh= 2.0 thus 1V drop with 20mA or 50 ohms for the PFET in the high state, worst case. This is by design to minimize shootthru currents \$\endgroup\$ Apr 11 at 17:07
  • \$\begingroup\$ who is the silent newbie -1? \$\endgroup\$ Apr 11 at 22:07

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.