I'm trying to measure relativistic speeds with an FPGA — are my results legit?

Question

I've been teaching myself FPGA programming in Verilog over the past year during the COVID-19 lockdown.

I found a discussion of whether it was possible to measure the speed of light using an Arduino or other microcontroller and the consensus was that the processor speed was too slow and there were too many outside factors like system interrupts.

I figured an FPGA would be well suited to this task and it would be cool to see if I could directly measure the speed of a signal through a wire, which moves at something like 0.85 the speed of light. I've gotten code working on a DE10-lite development board that does this, but I'm having some issues understanding the results. I'm really looking for feedback on whether my approach works at all and what to look out for.

My code is very straightforward. A state machine starts in IDLE until a button press moves it to state "COUNTING." In COUNTING an output wire "measure_outW" is raised from 0 to 3.3 V and then a 100 MHz always block increments a register ("measure_counterR)." This always cycle continues until an input wire (measure_inW), which is pulled down to ground by a 12 kΩ resistor, goes high. Measure_outW and measure_inW are connected through the test object, a long spool of wire. So the number of 100 MHz cycles it takes for the signal to travel from measure_outW to measure_inW (through the long spool of wire) is recorded by measure_counterR.

The state then moves to "REPORT" and the binary value in measure_counterR is converted to binary-coded decimal and fed to a UART which displays it on a PC. (I chose this setup just to get practice using a UART in Verilog.)

I used a fresh roll of 24-gauge wire-wrapping wire as a test object. It's advertised as being approximately 305 meters in length. I get values around 264 clock cycles for the travel time. Now this is with a PLL clock of 100MHz. Another roll of the same wire gives me values around 274 so I feel I'm really measuring something.

Question 1. Does an always block, that runs at posedge of a 100MHz clock, occur at 100 MHz or at 50 MHz (because it's just the posedge)? Sorry, I don't have a scope that can handle these speeds. If it's 100 MHz then in each clock cycle the signal moves 0.85 x (3x10⁸ m/s) * 1x10^-8 s) = 2.55 m. It takes 264 cycles to get through the spool so 2.55 m x 264 = 673 m. This is more than twice what I'd expect.

Question 2. Is it legit to measure very short time intervals this way? Does the PLL clock synchronize itself across the FPGA so everything is simultaneous? Or does it keep the phase across the device, at the expense of the actual absolute number of cycles?

Question 3. The values I get move around a bit, and are affected by the position of the spool of wire and its feed-in wires. I'm surprised it isn't a fixed number of clock cycles. Why does it vary by about + or - 10 cycles? I know oscillators can vary ("jitter"), but does this manifest over such short intervals (i.e., only 264 cycles)?

Question 4. I've measured two different spools of wire with different values. But when I combine them into one long test object the resulting time is a somewhat less than the sum of their individual times. Is there a capacitive or inductive effect happening? I'm just turning the line from low to high-- not sending pulses so it's not an AC signal.

Answer 1

You're measuring how long

1. The source current of your output pin

takes to charge up

2. The capacitance of your input pin

through

3. The inductance of your coil of wire

until it reaches

4. The threshold voltage of your input pin.

Number 3 is related to the length of your wire, but not as directly as you would think. It's also influenced by the geometry of the wire (the value you get with it laid in a coil like that is very different from the value you would get if it made a single 100m-diameter circle) and by the presence of any conductive objects nearby. Numbers 1, 2, and 4 have nothing to do with the wire you're testing; mostly they're fixed properties of the FPGA chip, but they are liable to vary several percent depending on things like your supply voltage and the ambient temperature.

Your experiment isn't impossible, but there are several things you would have to change before you stand any chance of measuring the thing you're trying to measure. Replacing the wire with coax (to reduce interaction with the outside world) and impedance-matching the whole system would be a first step.

You may also be interested in looking up time-domain reflectometry (in which only one end of the cable is connected to the measurement device, and the length can be found by looking for the reflection of the signal from the far end) and frequency-domain reflectometry (in which, instead of sending a single pulse down the cable, we send various frequencies of sine waves, and measure the magnitude and phase of the reflected signals relative to the original). The cost of that last one has come down quite a bit in recent years.

Answer 2

Just using a single wire isn't going to work for this -- basically, layer of winding on the spool talks to the next. Typically, you conduct this experiment with a good long length of coax cable; the measuring instrument can be a plain old oscilloscope. Then it's just a matter of trading off how much the measuring instrument costs vs. how much the roll of cable costs.

A 100MHz clock means one full cycle takes 10ns. So your "always" block should pop off 100,000,000 times a second. Note that 1ns is about a foot (convenient if you grew up measuring things in feet). If you do a lot of high-speed work, just memorize that (or 300mm, if that's easier).

So 10ns is about ten feet in free space.

100MHz clock means one full cycle in 10ns, or your "always" block popping off 100,000,000 times a second.

Until you do this using coax, or twisted-pair wire, differential signalling, and care to keep the wire at least somewhat spatially isolated, you're not going to get good results.

Answer 3

Does an always block, that runs at posedge of a 100MHz clock, occur at 100MHz

Yes, a 100MHz clock has 100M rising edges and 100M falling edges per second.

Is it legit to measure very short time intervals

The resolution is one clock cycle, or 10ns here, so how legit it is is up to you to decide, depending on the accuracy and resolution you need.

Does the PLL clock synchronize itself across the fpga so everything is simultaneous?

No, the clock propagates inside the FPGA along the clock lines.

Or does it keep the phase across the device

No, if there is signal propagation, then some points get the signal later than other, so there is phase shift.

at the expense of the actual absolute number of cycles?

This does not make sense. All the logic units in your FPGA get the same clock (if enabled) with a delay that depends on how much routing fabric it had to travel through.

"at the expense of the actual absolute number of cycles" is a decision you would make, since you choose the clock frequency so design can run properly accounting for all propagation delay. The PLL doesn't make design choices, nor does it skip cycles.

Question 3. The values I get move around a bit, and are affected by the position of the spool of wire and it's feed-in wires.

A single wire in a spool isn't a transmission line. There has to be a waveguide to constrain the wave into following the path you want it to follow along the transmission line. For acoustic waves, a pipe works well. For electromagnetic waves, consider coax, twisted pair, or even copper pipe but that only works at high frequency.

In your wire spool, the electromagnetic waves will jump from one turn of wire to the next without trouble, through the capacitance between wires, so why would they bother running in circle through all the turns when they can go straight?

Question 4. I've measured two different spools of wire with different values.

You're not measuring propagation speed, you're measuring capacitance.

If you want to play with this, you can buy a cheap roll of 75 ohm coax for TV antenna, or a spool of Cat6 twisted pair which has 100 ohm differential impedance. Pick the one you're most likely to reuse in the future for home improvement projects.

Answer 4

As others have noted, classical circuit theory effects (RLC) will overwhelm relativistic effects, making direct measurement from the FPGA impossible.

If you want to experiment, you can try building a Nutt interpolator. Background: here. Basically, create ratioed current sources and use the FPGA (asynchronously!) to control them, based on input events. The sources charge/discharge a capacitor, and the ratio of the currents effectively "stretches" the time interval to something the FPGA can measure.

Success will be constrained by how well you can match the current sources, as well as noise in the system. Likely you won't get anywhere near accurate results (these things are finicky) but it's a learning experience.