I've been teaching myself FPGA programming in Verilog over the past year during the COVID-19 lockdown.
I found a discussion of whether it was possible to measure the speed of light using an Arduino or other microcontroller and the consensus was that the processor speed was too slow and there were too many outside factors like system interrupts.
I figured an FPGA would be well suited to this task and it would be cool to see if I could directly measure the speed of a signal through a wire, which moves at something like 0.85 the speed of light. I've gotten code working on a DE10-lite development board that does this, but I'm having some issues understanding the results. I'm really looking for feedback on whether my approach works at all and what to look out for.
My code is very straightforward. A state machine starts in IDLE until a button press moves it to state "COUNTING." In COUNTING an output wire "measure_outW" is raised from 0 to 3.3 V and then a 100 MHz always block increments a register ("measure_counterR)." This always cycle continues until an input wire (measure_inW), which is pulled down to ground by a 12 kΩ resistor, goes high. Measure_outW and measure_inW are connected through the test object, a long spool of wire. So the number of 100 MHz cycles it takes for the signal to travel from measure_outW to measure_inW (through the long spool of wire) is recorded by measure_counterR.
The state then moves to "REPORT" and the binary value in measure_counterR is converted to binary-coded decimal and fed to a UART which displays it on a PC. (I chose this setup just to get practice using a UART in Verilog.)
I used a fresh roll of 24-gauge wire-wrapping wire as a test object. It's advertised as being approximately 305 meters in length. I get values around 264 clock cycles for the travel time. Now this is with a PLL clock of 100MHz. Another roll of the same wire gives me values around 274 so I feel I'm really measuring something.
Question 1. Does an always block, that runs at posedge of a 100MHz clock, occur at 100 MHz or at 50 MHz (because it's just the posedge)? Sorry, I don't have a scope that can handle these speeds. If it's 100 MHz then in each clock cycle the signal moves 0.85 x (3x108 m/s) * 1x10-8 s) = 2.55 m. It takes 264 cycles to get through the spool so 2.55 m x 264 = 673 m. This is more than twice what I'd expect.
Question 2. Is it legit to measure very short time intervals this way? Does the PLL clock synchronize itself across the FPGA so everything is simultaneous? Or does it keep the phase across the device, at the expense of the actual absolute number of cycles?
Question 3. The values I get move around a bit, and are affected by the position of the spool of wire and its feed-in wires. I'm surprised it isn't a fixed number of clock cycles. Why does it vary by about + or - 10 cycles? I know oscillators can vary ("jitter"), but does this manifest over such short intervals (i.e., only 264 cycles)?
Question 4. I've measured two different spools of wire with different values. But when I combine them into one long test object the resulting time is a somewhat less than the sum of their individual times. Is there a capacitive or inductive effect happening? I'm just turning the line from low to high-- not sending pulses so it's not an AC signal.