0
\$\begingroup\$

I'm using a TPS63060 regulator and according to its manual there should be typical 66uF capacitance on the output, please see this screenshot:

Typical setup

In order to achieve that I'm planning to use three 22uF capacitors plus one 1uF cap (as per TPS63060EVM, usually I use 100nF but in that EVM they're using 1uF for some reason, so I just follow that). My question is simple - should I put them all in one line and then connect load past these capacitors, like here:

inline

Or can I arrange them in this order ("checkerboard") to save some space? Would that affect any output characteristics? Thanks!

Checkerboard

UPD. After all the answers my final layout is this: Layout

And 3D view is here:

enter image description here

Having this board tested I've got less than 15mV ripple! Thanks to everyone!

\$\endgroup\$
4
  • 1
    \$\begingroup\$ If you can actually fit it, the bottom way is better because the loop formed by the output, each capacitor and the GND pin will be smaller. \$\endgroup\$ Apr 10, 2021 at 18:49
  • 1
    \$\begingroup\$ It will work fine either way, but don't trap yourself. You still need to route traces to the other pins on the regulator. The lower picture does not look practical as far as that goes. \$\endgroup\$
    – user57037
    Apr 14, 2021 at 16:01
  • 1
    \$\begingroup\$ If VCC_P4V5 is a plane or is changing layers, you need to leave room for lots of vias in the fill. \$\endgroup\$
    – user57037
    Apr 14, 2021 at 16:02
  • \$\begingroup\$ Thanks, the lower one has polygon extending to the right just to show the capacitor placement. I was more worried about if the capactiors should be in line, like when you're routing bypass caps for MCU - higher value ones first and then lowest value one closest to the pin, but in this case as it's an output of voltage regulator it looks ok to have them 'up/down' to the output. Thank you, I appreciate your help! \$\endgroup\$
    – Lt_Flash
    Apr 15, 2021 at 16:17

1 Answer 1

1
\$\begingroup\$

From an AC perspective there's no difference as the capacitors' distance is minimal (ignoring parasitic inductance of the trace). However, from a DC perspective it's much better to use the 2nd option as you have a wider trace which means less DC resistance.

\$\endgroup\$
1
  • \$\begingroup\$ Thanks, that's a perfect answer! \$\endgroup\$
    – Lt_Flash
    Apr 15, 2021 at 16:17

This site is temporarily in read-only mode and not accepting new answers.

Not the answer you're looking for? Browse other questions tagged .