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I'm trying to build a circuit that output an analog voltage proportional to the duration of a voltage pulse at the input like this:

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My idea is to charge a capacitor with a current mirror with a switch controlled by the input pulse.

I have build this circuit so far.

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But it has some issues that I would like you to help me with. Here is the output that I got:

enter image description here

First, I need it to start at 0V but it currently starts at 1.7V. I was thinking about shorting it to the ground when my input is at 0V but I don't know how to do it. Also I would like to control the slope because at this point, it is way too big and it even stops at 2.7V, I think it is because the transistors is not in saturation anymore.

Do you have any advice?

Thank you


So I managed to have a lower slope by increasing the capacitor to 5pF (max allowed values) and also by decreasing the current from the current mirror. Such that my slope stays linear even for impulse of width 250 ns (max values).

Also I got rid of the offset by adding a switch and an inverter like this:

enter image description here

Here is what I got as output:

enter image description here

Which is already better because it enables the circuit to work for successive pulses, as Vout is reset between pulses.

But the main issue is that I wanted to keep my output voltage constant once my first pulse is done and only reset it on the rising edge of the second pulse. And by adding the switch with M6, I don't have the holding principle anymore.

Anyone with an idea to fix it? Thanks

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  • \$\begingroup\$ The load pF and parasitic pF needs to exceed 1pF . What is the Cin and parasitic pF of the buffer for this signal ? The FET Coss must be minimized relative to the load. The offset voltage , I have to think about. For dV/dt=1V/10ns=Ic/C you have some other choices on transparent switches. The effective -3dB BW =0.35 / 8ns= 44MHz but for -0.? dB error BW is perhaps 10x more ! \$\endgroup\$ Apr 11, 2021 at 21:08
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    \$\begingroup\$ The circuit you need is an integrator. The voltage on the capacitor is an integral of the current through it. You are on the right path. In order to start the integration at 0v you need to short the capacitor to ground when the input signal is low - you can do that with an inverter and an nmos connected to the capacitor. As for the slope, is proportional to the current so you need to reduce the current to reduce the slope. \$\endgroup\$
    – Mike
    Apr 11, 2021 at 21:09
  • \$\begingroup\$ 1 pF is too small, rather than reduce current, increase load C \$\endgroup\$ Apr 11, 2021 at 21:13
  • \$\begingroup\$ What is the minimum rep rate for Int. & Hold? then rezero time error? i.e. what dV/dt and then dt or dV error for rezero is acceptable? \$\endgroup\$ Apr 12, 2021 at 0:00
  • \$\begingroup\$ By the "CMOS" in the question title I assume that this maybe homework for a VLSI course, and thus the transistors capacitances are probably much much lower than 1 pF. \$\endgroup\$
    – Mike
    Apr 12, 2021 at 5:55

1 Answer 1

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Blue is pulsed input signal, green is Cap voltage.

enter image description here

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Edit:

Regarding to one pulse only reset the 2pF Cap imediately after input pulse go low is undesirable so disconnect the Cap rather and reset is before next measurement only. For holding the voltage for longer time buffer it to bigger Cap. You can disconnect the bigger one after input signal goes low (+ charging time of big one) so it isnt affect by discharging the small one.

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  • \$\begingroup\$ Now try it for 10ns to 100 ns instead of 10 us !!! And have a hold after integration. \$\endgroup\$ Apr 11, 2021 at 23:55
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    \$\begingroup\$ It was just to show principle. \$\endgroup\$
    – user208862
    Apr 11, 2021 at 23:58
  • \$\begingroup\$ He already has an Integrate and hold principle. \$\endgroup\$ Apr 11, 2021 at 23:59
  • \$\begingroup\$ Thanks it looks great. Could you explain why the first slope is not like the others? Because the input signal is not supposed to be periodic, so only having the good slope after the first cycle might be an issue. @MichalPodmanický Also I should use 3.3 V as supply voltage and MOSFET transistors. Would it make any trouble? \$\endgroup\$
    – Saens
    Apr 12, 2021 at 10:55
  • \$\begingroup\$ @Saens The first slope is distored by initial Vrise of power supply in simulator. 3v3 using right Mosfets should be ok. If you are interested about just one period, maybe the shorting is necessary before mesurement only (to reset Cap). It depends on your aplication. You can disconnect the programing 10k leg to stop charging the Cap. \$\endgroup\$
    – user208862
    Apr 12, 2021 at 11:34

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