1
\$\begingroup\$

enter image description here

This is not a homework problem, I'm just revisiting/relearning the practical applications of latches and logic circuits and I've been trying to figure this out on my own.

Basically, I want to turn one input bit into three possible states of two output bits. When the input bit is "0", both output bits should also be "0". When the input bit is "1", one of the output bits should be "1" and the other should be "0". Which output bit is "1" should alternate every time the input bit is "1". I suspect this can be done with two SR latches and an inverter but I can't for the life of me figure out how... any ideas are welcome!

\$\endgroup\$
3
  • 1
    \$\begingroup\$ Output should change asynchronously (immediately) according to input or just at the clock edge? \$\endgroup\$
    – devnull
    Apr 12, 2021 at 22:34
  • \$\begingroup\$ Asynchronously. The input signal wouldn’t necessarily be an even clock, eg it might wait 4 seconds on “0” then switch to “1” \$\endgroup\$ Apr 13, 2021 at 0:01
  • \$\begingroup\$ Are glitches permitted? \$\endgroup\$ Apr 13, 2021 at 8:40

2 Answers 2

1
\$\begingroup\$

Try to use JK-flip flop with two AND gates. J and K input connect to Vcc and AND gates place on the inverted and non-inverted output. The outputs change everytime the input is one and when the inputs is 0 the AND gates turn off the outputs. Probbably the simplest solution.enter image description here

\$\endgroup\$
0
\$\begingroup\$

I don't know if simplest, but I would start with T flipflop https://www.allaboutcircuits.com/uploads/articles/Sneha_FF9.jpg then join the T and CLK together and AND the output with the T so the toggle flipflop will toggle on each transition on the input from the 0->1, but still have the output disable when the input 0.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.