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  • I have a tricky project that requires -10 V low, +40 V high, duty<0.5%, 2 kHz PWM.

  • Load: 50Ohm resistive (forward),backward is probably in MOhm range. max power 1W (only works with very low duty).

  • The most straightforward way I can think of: MCU driven dual supply complimentary MOSFET:

schematic

simulate this circuit – Schematic created using CircuitLab

  • However, the VDD+ and VDD- is so much greater than logic level, I wonder if this will blow up the MCU.

  • Is there better way to do this? I also checked half-bridge with 2 NMOS, but all schematic I found does not support dual supply (the low side is always grounded).

  • This is an isolated half-bridge driver I came up with. I don't know if it works:

schematic

simulate this circuit

  • Since VDD+ and VDD- are different, H-bridge is out of question.
  • Highly integrated solution is preferable.
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  • \$\begingroup\$ To turn off the PMOS, you need to apply a high voltage (30V) to the gate. The MCU cannot provide that, so you will need an extra stage for that anyway. How fast do you need the switching to be? The 10k pull-up might be too weak. \$\endgroup\$
    – polwel
    Apr 13, 2021 at 6:57
  • \$\begingroup\$ You can use galvanically isolated gate drivers for that, both N-MOSFET. Or using GDT transformer and few BJT transistors and zener diode. You can't directly drive this with a MCU and you should change logic level MOSFETs. \$\endgroup\$ Apr 13, 2021 at 7:02
  • \$\begingroup\$ @polwel <1us, thanks for pointing out the obvious, can't believe I missed that. \$\endgroup\$
    – 7E10FC9A
    Apr 13, 2021 at 7:04
  • \$\begingroup\$ @MarkoBuršič Could you please show an example circuit ? I cannot find any half-bridge gate driver that accepts dual supply. \$\endgroup\$
    – 7E10FC9A
    Apr 13, 2021 at 7:07
  • \$\begingroup\$ Any two isolated gate drivers can do that. But that's expensive solution. Why do you need this circuit anyway? PWM frequency, PWM max. min. duty cylcle, max. current, load type? \$\endgroup\$ Apr 13, 2021 at 7:29

3 Answers 3

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First of all is not that a gate driver will necessary blow the MOSFETs… depending on the part the 'logic level' indication is simply to say that the Vgs(th) is low enough to do some useful switching even with a logic level signal. Many of these are in fact rated at both 4.5V and 10V gate drive. Of course there are MOSFETs with Vgs(max) of 8V and maybe even less so it's wise to check the datasheet.

You can also do a simple gate drive with a trivial class B transistor pair. The issue is if you need a push-pull gate drive (recommended for PWM) or you only need a pull down and let it go back with the pullup resistor (for the high side, the converse for the low side). That's difficult to evaluate without the exact specification, gate charge and at least an estimate of the dissipation in the MOSFET (switching losses will be predominant in this case).

The top side is usually the difficult part but not in this case. Your schematic will potentially apply the 30V to the GPIO (altough thru a 10k resistor); in practice if will probably work but it isn't wise (neither it is good practice). Also you will be applying 30V of Vgs to the P-channel MOSFET and you probably don't want that. A zener would fix that.

Just pull from somewhere an 'adequate' gate drive voltage (the power rail with a zener) and a pair of transistors.

The low side is somewhat tricky, but remember that 'ground' is a subjective term. You can simply anchor your drive circuit to the -10V as ground. Your original ground will then become a +10V supply, which is great for driving gates (or use some regulator to get a -5V rail, if you are Vgs constrained).

Now the problem is shifted: you have a correctly driven low gate but you need a -10V to -5V (assuming a 5V logic) driver control. However, this is not so critical as timing so you can use a pullup resistor (as an aside: real translating drivers use a latch and two translation lines, but they are ICs). Either use a suitable optocoupler (easiest way) or use a current line to translate the level.

schematic

simulate this circuit – Schematic created using CircuitLab

Something like this should more or less work; the drive pair are often implemented as BJTs, it doesn't really matter at these power levels. Be careful with the low side drive polarity: the translation line will invert it! Also verify biasing extremes, I didn't really thought through all the circuit, it's most like an idea to work on.

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  • \$\begingroup\$ Thanks for answering ! Actually, I prefer ICs and optocouplers, the circuit you provided has too many external parts, and too complected to prototype for me. Of course the FETs can be changed. I bought the logic-gate FETs because they have very fast switching time. \$\endgroup\$
    – 7E10FC9A
    Apr 13, 2021 at 7:30
  • \$\begingroup\$ Those MOSFETs buffer pairs are going to cross conduct and the zener D1 with 100ohm resistor wold dissipate quite lot of power. Not so easy. \$\endgroup\$ Apr 13, 2021 at 7:35
  • \$\begingroup\$ It was an example, the details need to be established. However such circuits are widely used in practice (with BJTs, usually) \$\endgroup\$ Apr 13, 2021 at 7:43
  • \$\begingroup\$ Logic level MOSFETs are usually even faster when using a standard drive, the gate simply fills faster (of course if they handle it). 10V is a conventional value, you usually see them driven with 12 or even 15V (15V IIRC is the IGBT standard drive) \$\endgroup\$ Apr 13, 2021 at 7:45
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I assume you mean "IR2104" and not "IRL2104". Using a gate driver chip is indeed a simple solution, but it will not work like this:

enter image description here

Basically, from the point of view of the driver:

  • Its "GND" pin sits on -10V

  • Its VCC should be connected to a 10..12V supply, which from its point of view is "VCC" but you and the rest of the circuit calls it "GND" since it is 10V above the -10V.

  • "+40V" just appears as "+50V" to the chip.

Like you wired it, the VCC has +12V, but relative to circuit ground, not to the -10V that this chip calls "GND", so it is supplied with 22V. It will withstand this, but it will send this voltage on the FET gate, which is only rated to 20V usually, so it will probably blow the gate of the FET.

Solution is simple:

Move the following pins from +12V to GND:

  • IR2104 VCC pin

  • VCC side of its decoupling cap

  • Anode of the bootstrap diode. Where is it, by the way? It won't work without a bootstrap diode. Look at firts page of datasheet, and use a fast diode or a Schottky, rated for the voltage, say 50V plus margin, ie 100V.

Also you can get rid of the very slow optocoupler which will interpret your duty cycle in its own creative manner. It is wired to the wrong voltage anyway and you forgot the pull resistor on the output. Just use a level shifter instead. There is nothing wrong with using 3c worth of parts when it works better than an opto ;)

enter image description here

This outputs a signal that is referenced to the -10V that the driver uses a reference.

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  • \$\begingroup\$ The optocoupler is actually quite fast. HCPL-7721 only 40ns propagation. \$\endgroup\$
    – 7E10FC9A
    Apr 13, 2021 at 14:56
  • \$\begingroup\$ That would work, but it's a lot more expensive than a MMBT3906. \$\endgroup\$
    – bobflux
    Apr 13, 2021 at 15:40
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0.5% duty cyle of 2kHz is 2.5us pulse.

schematic

simulate this circuit – Schematic created using CircuitLab

BUF 1 and 2 are gate drivers, you do need 12 to 15V to supply them. The transformers are GDT 1:1. You could even change the buffers with a push-pull MOSFETs.

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  • \$\begingroup\$ Why not use half bridge driver, which have build-in dead-time, instead ? Also what's the purpose of the circuits between isolation transformer and the FETs ? \$\endgroup\$
    – 7E10FC9A
    Apr 13, 2021 at 12:34
  • \$\begingroup\$ You haven't provided any details about the output waveform. This circuit is suitable for very short pulses, some microseconds as you described. Those are for fast turn off. It can be even without it, or using a pair of zener diodes, or a resistor. \$\endgroup\$ Apr 13, 2021 at 12:55

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