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A basic cmos inverter will have a P-transistor upside and N-transistor down side. what happens if we reverse the p and n transistors?

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    \$\begingroup\$ They become CMON transistors (Complimentary Metal Oxide Neverconductor). \$\endgroup\$ – Olin Lathrop Jan 24 '13 at 14:07
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Nothing will happen. Neither transistor will be able to turn on.

The N-channel enhancement-mode transistor requires its gate to be at a higher voltage than the source (or drain), which can't happen if it's connected to Vcc.

Similarly, the P-channel transistor requires a negative voltage on its gate, which can't happen if it's connected to ground.

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  • \$\begingroup\$ If you want to thank me, upvote the answer and accept it. (Although, to be honest, we generally encourage waiting at least 24 hours to accept, in case a better answer comes along.) \$\endgroup\$ – Dave Tweed Jan 24 '13 at 14:09
  • \$\begingroup\$ Nope, they should still be able to turn on. But the issue is very visible in the two other answers. The buffer won't be able to have rail-to-rail output levels due to the threshold voltage. \$\endgroup\$ – Oskar Skog May 11 '17 at 14:27
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Unloaded outputs:0.18u process using Thick Oxide (0.35u transistors) Input is a 1us slow ramp and decay to show transitions, other line is the output of the inverter and green line is the strange case with PMOS and NMOS flipped with bulk connection as per normal.

simulation

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  • \$\begingroup\$ You need to add an explanation of what these graphs represent. I can guess, but I shouldn't have to. \$\endgroup\$ – Dave Tweed Jan 24 '13 at 23:17
  • \$\begingroup\$ @DaveTweed context is an input, inverter output and the flipped NMOS and PMOS as per the original question. \$\endgroup\$ – placeholder Jan 24 '13 at 23:25
  • \$\begingroup\$ Is there any load on the output, or is it just floating? How much current is actually flowing in the transistors? What simulator did you use? \$\endgroup\$ – Dave Tweed Jan 24 '13 at 23:38
  • \$\begingroup\$ @DaveTweed What you are seeing is sub-threshold behaviour emphasized by DIBL, GIDL and the back gate effect. The assymetry is due to the fact that the transistors are sized differently PMOS 2X) for active mode operation, in sub-threshold they tend to be better balanced in W/L. Simulator is a production simulator using foundry decks. The flipped version falls under the classification of a trans-linear circuit, it would be acceptable to use in low voltage situations. I'll run other sims later and add a 0.65 rail version. It will be interesting. \$\endgroup\$ – placeholder Jan 24 '13 at 23:48
  • \$\begingroup\$ I will not be adding like I said above, as it takes it too far away from the original intent of the question. \$\endgroup\$ – placeholder Jan 25 '13 at 3:17
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Like this?

CMOS nonverter

At first glance, this looks like it could be a CMOS buffer: T1 = T2. You'd think that the channel would be opened or closed by the voltage difference between the body and the gate, regardless of what the drain and the source are doing.

I built this thing with a CD4007UB. You do get an output signal in phase. But it's err...weird. My scope is analog, so I don't have a good way to give you a picture, but Vcc was 5V, and I gave it a 5V p-p 1kHz square wave input. The output was a square wave in phase, with sharp rises but very slow falls. The low output was at 0V, but the high was only about 2.5V.

I'm an amateur electrical engineer, not a physicist, so I can't explain all this behavior, but from other's comments and what I've learned from my own research, I have a pretty good guess of what's happening here. Check out this diagram of MOSFET operation from Wikipedia's page on MOSFETs:

MOSFET operation

If you see in the bottom two images, the conductive channel in the middle doesn't go all the way across. However, some charge carriers (electrons or holes for N and P channel MOSFETS, respectively) are still able to sneak across by some physical reason I don't fully understand. The reason it's pinched off here is that the width of the conducting layer is a function of the voltage difference between the gate and what's near it, and for most of the gate, that's the body. But near the pinched off end, the gate is near the drain. Unless you can get the gate \$V{th}\$ above the drain, you can't open the channel all the way across.

Ordinarily, once you get it close, then some current can flow. Once that starts to happen, the voltage across the load connected to the drain increases, and consequently, the voltage at the drain must decrease. This opens the channel a bit more, more current flows, and so on, until the drain voltage is at its minimum, the channel is as wide as it can get, and the transistor is fully on.

Problem is, in this circuit, the gate can't get significantly higher than the drain or the source. So even though there's a conductive channel in the middle, it's pinched off at both ends, and what you are left with are two P-N diodes in opposite directions. No current can flow.

That's my guess. I suspect asymmetries in the manufacturing of N and P channel devices, and the less than perfect calibration of my test equipment explain why it sort of works a little, asymmetrically.

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  • \$\begingroup\$ You have a point: The conductive channel in an N-channel MOSFET is formed when the gate-substrate bias modifies the distribution of electrons in the depletion region that forms under the gate to the point where some of them are in the conduction band. However, this is where I'm out of my depth on the physics. It can't work the way you're thinking, or else CMOS transmission gates wouldn't need both N-channel and P-channel devices; just an N-channel device would be enough. But I don't know what the reason is. \$\endgroup\$ – Dave Tweed Jan 24 '13 at 15:59
  • \$\begingroup\$ @DaveTweed I think you do need P and N channel devices, even so. How else would you make a CMOS totem-pole? You could do RTL with just N-channel MOSFETs, but what would be the point of that? \$\endgroup\$ – Phil Frost Jan 24 '13 at 16:13
  • \$\begingroup\$ OK, I looked it up in my college textbook. When the gate and drain/source are at the same potential, the channel is "pinched off" at that end. In normal operation, with the source connected to the substrate, this pinchoff occurs only at the drain end, and the drain voltage at which this occurs marks the transition from linear mode to saturated mode. But if the source is also at the gate voltage, the channel is pinched off at both ends, and no current can flow, even if there's an inverted channel near the center of the gate. \$\endgroup\$ – Dave Tweed Jan 24 '13 at 16:39
  • \$\begingroup\$ @DaveTweed I'm having a hard time getting my head around that without a picture, but I'll get a good empirical answer to the question when I build it tonight. \$\endgroup\$ – Phil Frost Jan 24 '13 at 19:41
  • \$\begingroup\$ @DaveTweed built! You are right...it doesn't really behave predictably. But it does do something. \$\endgroup\$ – Phil Frost Jan 25 '13 at 2:15

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