I have a Lattice FPGA-targeted design which already takes approximately 95% of the SLICEs available on the device; pretty close to the chip capacity. Unfortunately, I need to add some more logic to it, so I have to optimize things a bit. But how do I identify the most problematic parts of the design? Neither “Network Analyzer” nor “NCD View” tool can give me such data. The best thing I found so far is to filter the NCD View list against a specific module name and manually count all the cells it shows. I believe there must be a better way.

Did I overlook some obvious option or dialog?
Can Lattice Diamond generate a detailed report on device utilization?

Related question (specific to the Xilinx software):
How to identify areas of a FPGA design that use the most resources and area?


1 Answer 1


You are mostlikely looking for the "Hierarchy – Post Synthesis Resources" view. In my version it is "hidden" as a tab next to the "File List" and "Process" views.

  • 1
    \$\begingroup\$ Thank you, I really overlooked that window. Unfortunately, it won't show anything useful if the project contains even a single line of SystemVerilog code (“No Hierarchy could be parsed out because there is System Verilog in project”). \$\endgroup\$ Apr 14, 2021 at 9:44
  • \$\begingroup\$ oh that is an interesting information I was not aware of. Good to know! \$\endgroup\$ Apr 16, 2021 at 19:47

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.