CMOS (wrong) OR gate with 4 transistors

I'm currently reading through Introduction to Computing Systems: From Bits & Gates to C & Beyond and I'm a bit confused about the outputs of this OR gate (which is not an OR gate):

And here is the provided text:

I guess I could imagine, that there is something like "voltage drop" in the case when either or both of the inputs A, B are 1.2 volts. That is, the nMOS transistors connected in parallel act like a "closed" switch and they will be "on", but because of the "transmission voltage", the output at C will be 1.2V (from the source) - 0.5V (the "voltage drop") = 0.7V.

I'm not even sure if this is the correct interpretation, but so far the book provided only this kind of abstraction as "closed" or "open" switch.

Why I don't really understand is that, when the both inputs A and B are at 0 volts, how come the output is 1.0 volts? If the input is 0V, then both nMOS transistors connected in parallel in the upper part of the diagram will be in the "off" state, meaning that they will behave like an "open switch". No current will pass through them. In the case of pMOS transistors, if the input is 0V, they should be "on" and act like "closed switch", so that means there will be path from C to the ground. How come the output is 1.0V?

If I may ask so stupidly: pMOS is connected to the ground, on the input there is 0V, and the source is "disconnected" (since the nMOS will act as open switch), how come there is "magically" 1.0V at the output?

Thank you all very much!

• Maybe it's assuming some kind of open collector configuration? That is, the output is connected to a pull up resistor. Then you'd see a voltage at C. Apr 14, 2021 at 11:53
• The reason why CMOS logic is so power efficient, easy to use and has sensible voltage levels (0 = 0 V, 1 = Vdd) is because the MOSFETs are used such that when a MOSFET is switched on, it will have a Vgs = Vdd (or -Vdd for a PMOS) and Vgs = 0 when switched off. This circuit goes against that and isn't even worth to be called "logic" or "gate". It could have some analog function but for sure it cannot operate as "proper logic". Suggesting that in a textbook on logic circuits will only confuse students. Apr 14, 2021 at 14:11

That's a pretty bad explanation in the book.

MOSFETs have a threshold voltage. This is the minimum voltage difference between the gate terminal and the source terminal that will allow the transistor to conduct significant current. For an NMOS transistor, the threshold voltage is a positive voltage, and the "source" terminal is defined to be which ever of the source/drain terminals has the lower voltage.

So, in your circuit the NMOS transistor drains are connected to 1.2V and their sources are connected to the gate output. If you bring the gates of these NMOS transistors to 1.2V then the transistors will only conduct current as long as their sources -- the OR gate output -- have a voltage that is not higher than 1.2V minus the transistor threshold voltage. Once the OR gate output rises to $$\(1.2 - V_{TH})\$$V the transistor stop conducting very well, so the OR gate output stops rising.

The same analysis applies to the PMOS, except that the source is defined to be the terminal with the higher voltage and the gate must be at a lower voltage than the source for good conduction.

EDIT: When one of the OR gate inputs is at 0V, we have an NMOS transistor with its gate at 0V so it is certainly not going to conduct significant current. We also have a PMOS transistor with its gate at 0V...its source is connected to the OR gate output and its drain is connected to ground. So, if the OR gate output is at 1.2V then the gate-to-source voltage for the PMOS will conduct current, bring the OR gate output voltage lower. When the OR gate output voltage falls to the point that the gate-source voltage of the PMOS is less than its threshold voltage, then the PMOS stops conducting. This leaves the OR gate at a voltage approximately equal to the magnitude of the PMOS threshold voltage.

• Their text book is made from someone that isn't very adept in the design of logic gates. The description of operation in the text book seem to be for transistors, but foolishly using slang to describe PNP and NPN transistors, and confusing others because it so close to the common terms for MOSFETs. If they were MOSFETs, why are they not describing modes (depletion/enhancement) ? Apr 14, 2021 at 12:57
• @DavidMikeska CMOS logic gates always use enhancement mode devices, at least in my experience. That's mentioned on page 1 and then never mentioned explicitly again. Apr 14, 2021 at 13:12
• Thank you very much for your answer. Could you please elaborate what will happen if both inputs are 0V? I still don't think I understand how is the output at 1V. I've tried to simulate the circuit in falstad.com/circuit-java but I still get different outputs then in the book. Thanks :) Apr 14, 2021 at 14:25
• @DavidMikeska depletion mode MOSFETs are pretty rare as well. Apr 14, 2021 at 17:04
• Not really @MissMulan they are just rare in some designs, and no one will know exactly what a gate designer will use to make their die, they just have to make it conform to what industry number it is assigned. I notice they are still producing them. Even in surface mount. The last one I encountered was the power/reset circuit in the Raspberry Pi. But it kind of goes with the saying, the designer could use anything they want to design the circuit. Especially if it can be built with less expense. Apr 14, 2021 at 18:48

This 'bad' explanation has come up before... and my take on it here: Why are the voltages the way they are in this transistor circuit? There's a simulation you can try out.

And here it is, again NAND Gate Sim

• what's shown is a NAND gate, with P and N in the wrong places.
• It's wrong because P-FETs need Vgs to be negative (that is, gate voltage below source by at least the threshold voltage) to turn on properly, the opposite of N-FETs which need Vgs to be positive to turn on.
• The 'wrong' circuit can only bias the transistors 'off' (with leakage), or in the linear region as a source follower.

About that latter point. Look at the sim and mouse-over each transistor in the 'wrong' circuit, noting what Vgs is doing. You'll see the transistors in one of two states: completely 'off', or biased in the linear region at the threshold voltage.

(In this sim, Vgs threshold is set to 700mV.)

The reason for there to be any voltage at all is that even when 'off', the FET still has leakage. The 'off' FETs behave as a high value resistors to the ones that are 'on', behaving as source followers. Meanwhile, the 'on' transistors biased as followers will go to the Vgs threshold voltage, but no further.

The output voltage changes somewhat with the input state because, depending on the input values, the transistors will be in 'off' leakage state or in source-follower state.

Unlike their table however, the highest voltage occurs when both inputs are high, and the lower series-connected P pair are both in the 'off' state behaving as high-value resistors.