And here is the provided text:
I guess I could imagine, that there is something like "voltage drop" in the case when either or both of the inputs A, B are 1.2 volts. That is, the nMOS transistors connected in parallel act like a "closed" switch and they will be "on", but because of the "transmission voltage", the output at C will be 1.2V (from the source) - 0.5V (the "voltage drop") = 0.7V.
I'm not even sure if this is the correct interpretation, but so far the book provided only this kind of abstraction as "closed" or "open" switch.
Why I don't really understand is that, when the both inputs A and B are at 0 volts, how come the output is 1.0 volts? If the input is 0V, then both nMOS transistors connected in parallel in the upper part of the diagram will be in the "off" state, meaning that they will behave like an "open switch". No current will pass through them. In the case of pMOS transistors, if the input is 0V, they should be "on" and act like "closed switch", so that means there will be path from C to the ground. How come the output is 1.0V?
If I may ask so stupidly: pMOS is connected to the ground, on the input there is 0V, and the source is "disconnected" (since the nMOS will act as open switch), how come there is "magically" 1.0V at the output?
Thank you all very much!