I'm having trouble with a comparator from TI (LMH7322). I use it in the circuit shown in the attached image "Comparator_1"Circuit as implemented.

Outputs go to an FPGA. The circuit is supposed to take a single ended input signal (VG2), which is between +/- 1V at up to 80MHz, and turn it into an LVDS signal. The TINA simulator gives a constant output in the configuration shown (1.4V on VoutB and 1.0V on Vout). In reality, both Vout and VoutB are at 1.8V, with noise at a frequency matching the input (VG2) frequency. I thought the simulator was wrong and I found that shifting all voltages up by 1.6V (as in "Comparator_2"All voltages shifted up by 1.6V) makes the simulator work (note the "false_ground" net and VS6 voltage).

I therefore think the simulator has a problem.

The outputs QOUT and QBOUT The datasheet for the part (LMH7322 datasheet) states that QOUT and QBOUT should have levels VCCO-1.5V and VCCO-1.1V or VCCO-1.1V and VCCO-1.5V. Note that my setup is as per the datasheet's Figure 11 with VCCI and VEE set to +/-3.4V respectively.

So I have two questions: Do you agree that the issue shown by the simulation is really a problem with the simulation model? Why would the outputs of the comparator be both at 1.8V rather than 1.0V or 1.4V?

Edit: The outputs go straight to the FPGA pins and the termination resistor (R3) is close to these pins. The FPGA is an Altera Cyclone IV. The FPGA pins are on a bank whose I/O voltage is 2.5V (as required for LVDS on this FPGA) and the pins are set as LVDS inputs.

  • \$\begingroup\$ Post link to image and we'll edit it in. \$\endgroup\$
    – AndrejaKo
    Jan 24, 2013 at 16:56
  • 1
    \$\begingroup\$ A schematic of how you connect to your FPGA might also help. Most current FPGA's will have trouble with inputs above 3.3 V. Also, +1 so you can add images now. \$\endgroup\$
    – The Photon
    Jan 24, 2013 at 16:59
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    \$\begingroup\$ Your circuit shows only one connection to the "true" ground. Therefore, the only way that varying VS6 could affect the behavior of the circuit is if there's another implicit connection to ground somewhere, perhaps inside the LMH7322 model itself. \$\endgroup\$
    – Dave Tweed
    Jan 25, 2013 at 12:15

2 Answers 2


Now fixed. The LMH7322 has ECL outputs. It is capable of providing LVDS levels, but this is not true LVDS. The outputs therefore need termination to ground (or another voltage below VCCO-2V).

I replaced the single 100 ohm termination resistor between the outputs with two 50 ohms, each to ground, and now the output is as expected. There are therefore a couple of problems with the model in the simulator: the device works fine with VCCI at +3.4V (as in first figure) and the model does not model the outputs as ECL.

Thanks to all for your comments.


I had the same simulation issue as described above (constant output, no toggle). Instead of shifting all voltages by +1.6V it seems sufficient to shift only the negative input level IN- to +1.2V DC. This is not the behaviour of the circuit I see in reality. It could point to a problem in the spice model.


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