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I'm currently redesigning the signal propagation algorithm of a circuit simulator I'm developing as a hobby project (https://www.antarescircuit.io).

In the new design, I'm trying to detect when conflicting signals are asserted to wires and issue a warning if this is the case. Now I get lots of warnings when simulating the famous MIC-1 machine according to "Structured Computer Organisation" by Andrew S. Tannenbaum. They originate from bus contention when reading register values from the CPU's scratchpad (aka register file).

The scratchpad circuit looks as follows:

Scratchpad

The tristate buffers at the right side are supposed to control which register forwards its current value onto the CPU's B data path. The register is selected by 4-bit input "FB", whose value gets decoded by an 4-16 decoder.

The problem is that the decoder (like any combinational circuit) produces intermediate results due to propagation delays of the various logic gates it consists of. In the example above, register 6 is to be addressed, but for a short moment, the decoder sets more than one output line to "high".

The contention exists for 20 ns and is determined by one single gate delay. I've chosen this value for simulation because it seems to be in the range of typical real hardware gates. The signal then remains stable for at least 9'000 ns.

The root cause the contention is illustrated by the following snapshot of the decoder. The signals that run through the inverters take longer, and the output AND gates produce invalid intermediate results.

Note: The snapshot is taken from a test with a 3-8 decoder. The 4-16 decoder used in the scratchpad consists of two of them. And don't be confused by the "zero" bubbles at the AND's outputs. These are produced by the signal flow animation feature and represent the signals that are going to flow to the outputs with the next simulation cycle, thereby establishing the expected and correct output of the decoder.

Decoder

The question is how conflicting signals at the outputs of tristate buffers can be avoided. I've considered the following options.

  1. Fine-tune timing: Add non-inverting buffers with the same propagation delay like the inverters to the decoder to make sure that all signals arrive at the AND gates at the same time. This makes the simulation work correctly, but looks to me like cheating, and I'm not sure if this would really eliminate the problem on real hardware, where you would face varying propagation delays due to fabrication differences of the logic gates.
  2. Synchronization: I understand that combinational logic generally produces intermediate results, and clocked circuits are generally used to deal with that. However, neither Tannenbaum in his book mentioned this problem when he explained the scratch pad, nor could I find information on the net that discusses whether it is legitimate to directly control tristate buffers with the output of combinational decoders. Trying to synchronize the output of the decoder would require significant change in the micro architecture of the CPU, probably involving the need to introduce another sub-clock signal.
  3. Ignore the problem: I could easily ignore the problem, as the simulated CPU circuit works fine despite the temporary bus contention. However, I'd like to do that only if my design of the scratchpad is reasonable, and it is common to ignore such short and temporary contention situations, even when running the circuit on real hardware. But since these situation, at least in my understanding, represent temporary "short circuits" on real hardware, I doubt that these are acceptable.

I'm more a software engineer than an electrical engineer and am therefore perhaps just not aware of a possibly obvious solution to my problem, so any help is appreciated.

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  • \$\begingroup\$ The first thing that comes to mind is to use the enable pin. Disable output, change data input to selector and enable it. \$\endgroup\$ – Justme Apr 15 at 8:50
  • \$\begingroup\$ @Justme Yes, that's basically what I meant with option "2. Synchronization". In order to calculate the "enable" signal, I would probably have to derive another clock sub cycle signal from the CPU's main clock. If this is the way to go, I wonder why Tannenbaum didn't include this signal in his microarchitecture. Perhaps he considered it a "minor aspect" and didn't want to bloat the textbook for educational reasons? \$\endgroup\$ – andreasfl Apr 15 at 10:38
  • \$\begingroup\$ In order to decide whether this is really a problem or not, you need to tell us how long "short" is. Exactly how long is the period of time when you have contention on the bus, compared to the typical rise and fall time of signals on the bus? \$\endgroup\$ – Elliot Alderson Apr 15 at 11:26
  • \$\begingroup\$ @ElliotAlderson The contention exists for 20 ns and is determined by one single gate delay. I've chosen this value for simulation because it seems to be in the range of typical real hardware gates. The signal then remains stable for at least 9'000 ns. \$\endgroup\$ – andreasfl Apr 15 at 15:08
  • \$\begingroup\$ Do you know what the rise and fall time are for the bus? If the rise and fall time are significantly longer than the contention time then the contention won't matter much. \$\endgroup\$ – Elliot Alderson Apr 15 at 15:43
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If the time of contention is short, compared to the time it takes the bus to change from high to low (the fall time) or from low to high (the rise time) then the contention is not usually significant.

For example, suppose a wire in the bus has been driven to a high level by driver A. Once the wire reaches that high level then driver A is sourcing only a tiny current to keep it there. Now, if driver B starts to try to drive the wire low then driver B will be sinking a large current to change the voltage on the wire quickly. However, most of that current is from discharging the capacitance of the wire rather than from driver A. Driver A is still supplying only a tiny current at first. As long as driver A gets turned off before the voltage on the wire falls very much, the bulk of the current through driver B will be from discharging the bus capacitance (which can not be avoided) and not from contention with driver A.

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