Here the schematic of a small board with a 74HC595 shift-register:
Here the detail of each output. They are connected to QB..QE.
Nothing is connected to the collectors of BJTs and the board contains no other components. The signals (SER and SRCLK) come from an external MCU that drives the lines with an optocoupler.
The MCU takes care of the correct output bits and the common "trick" to derive the RCLK signal from the last clock bit.
On my bench all works like a charm. I have several boards (and several MCUs) and all is fine. But the very same setup tested on a customer's system leads to a weird behavior: when there is at least one bit enabled, sometimes also other outputs go high.
I checked with the oscilloscope to find some spikes or other noise (the system is surrounded by a lot of DCDC converters):
The signals seems quite clean to me. To set a bit high a spike should be reach more than 3V during the clock edge. Please note that if I send all zeros it never happens that an output goes high. If the noise would be there, it should act regardless the actual data.
What if this is an xy problem? I mean, what else can lead to an high level on the outputs other than put the SER signal high during the clock edges?