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In this video from Ben Eater, he uses an RC circuit to create a push-button "write-pulse" generator for his EEPROM (discussed around the 14 minute mark) that ensures the write pulse fits within the timing requirements from the datasheet.

The schematic for the circuit is:

schematic

simulate this circuit – Schematic created using CircuitLab

However, I am at a loss understanding how this circuit works. Ben states in the video that the 1k resistor is to allow the capacitor to self-discharge, but to me it looks like there is no way for current to flow out of the capacitor when the push button is open, as both ends of the capacitor are tied to +5V through the resistors. I also don't understand how the capacitor gets emptied for the next time the button is pushed.

So how is it that this circuit is able to create the single inverse spike for the write-pulse that is seen on the oscilloscope in the video, and what exactly does the 1k resistor do?

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  • \$\begingroup\$ If there is no R1, all you have is a series R2 + C after the switch is opened. With R1, you have a parallel resistor. You still have it even when the switch is closed. \$\endgroup\$ – a concerned citizen Apr 15 at 18:52
  • \$\begingroup\$ @aconcernedcitizen So then when the switch is opened, the voltage source becomes irrelevant and can be ignored, and the current flows in the loop with the two resistors and the capacitor? \$\endgroup\$ – stix Apr 15 at 18:54
  • \$\begingroup\$ No, the cap is still discharged and will be charging, but only for a short while. It will peak above the supply, though, if the output is to the right side of C. Small test (which you could have done it yourself, free simulator on this site). \$\endgroup\$ – a concerned citizen Apr 15 at 18:58
  • \$\begingroup\$ @aconcernedcitizen That just leaves me more confused. Where is the current flowing to out of the capacitor when the switch is open then? \$\endgroup\$ – stix Apr 15 at 19:04
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The current flows in two paths, One when the switch is closed and then reverse when the switch is open (while C1 has charge in it).

When the switch is closed at t0, C1 has no charge, and so acts as a short circuit. So at t0 the output will be effectively connected to ground. As C1 charges up, the voltage at output will go up to 5V and thus you get an inverse pulse.

schematic

simulate this circuit – Schematic created using CircuitLab

When SW1 is open, then C1 can self discharge through R1 and R2.

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Sigh. Another bad Ben Eater thing.

The way this works:

  • Initially, the cap is initially discharged through R1 and R2 and is at 5V. The output is also at 5V.
  • Close the switch, the discharged cap is instantly brought to ground. This brings the right side - the output - to ground as well.
  • While the switch is still closed, the cap charges up though the 680 ohm to the supply voltage. The charge-up time is 1.1RC, or about 750ns.

Now, here's yet another reason why Ben Eater videos are such dumpster fires:

  • When the switch opens, the 1k pulls up the left side of the cap rapidly. Meanwhile, the right side - the output - goes over 7V, then discharges back to 5V through the 680 and 1k.

Guess what? You just fried your chip (or if you hit it enough times with that positive spike, you eventually will.) Why? 7V (Vcc + 2.0V) is the Absolute Maximum Rating for any I/O on this chip, and this circuit exceeds that. Further, the Recommended Operating Conditions states that Vi(h) should be Vcc + 0.3V maximum.

What that means is, the chip manufacturer doesn't want the ESD protection diodes to come into play unless, you know, the chip is in need of protecting from an actual ESD event.

In short, Ben Eater has shown you a bad design that stresses the chip.

Here's something that won't do that (simulate it here):

enter image description here

The diode clamps the positive-going voltage on button release so that it won't get to the chip and damage it.

You can argue all you want that the chip itself has protection, but it may not be enough, and when push comes to shove, the manufacturer's data sheet is the governing document. Without the catch diode this pulse gen is marginal, and out of both Absolute Maximum and Recommended spec.


Oh, and one more thing: Switch bounce. Ben got lucky with his sample (or at least what he was willing to show on video), but in the real world? They will oscillate for some milliseconds before they settle down. More here: https://www.allaboutcircuits.com/technical-articles/switch-bounce-how-to-deal-with-it/

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  • \$\begingroup\$ nearly 10 for large values of 7, and the eprom, probably already has that diode. \$\endgroup\$ – Jasen Apr 15 at 19:47
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    \$\begingroup\$ If an engineer worked for me and they proposed counting on the input protection diode for catching a spike like this, they wouldn't be working for me for very long. \$\endgroup\$ – hacktastical Apr 15 at 19:52
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    \$\begingroup\$ If chip I/O protection diodes are so great (narrator: they aren't), the whole product category of fast-acting TVS devices would be unnecessary. Now ask yourself: when your systems are dying in the field and the fault is traced to overstressing the chip pad, do you want to be the (likely junior) engineer explaining to the FA person in the exec meeting why you thought this crappy circuit you got off YouTube was a good idea? \$\endgroup\$ – hacktastical Apr 15 at 20:41
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    \$\begingroup\$ Your error is that R2 = 680R, not 680k. \$\endgroup\$ – James Apr 15 at 21:00
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    \$\begingroup\$ @James thanks - I revised the sim and text. Still bad - over 7V without the diode. \$\endgroup\$ – hacktastical Apr 15 at 21:45
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Prior to switch closing both sides of cap at +5V.

Switch closes, both sides of cap instantly drop to 0V then RHS of cap charges to +5V via R2.

Switch opens, RHS of cap instantly jumps up to approx +7V and LHS of cap instantly jumps up to approx +2V. (There is momentarily still +5V across the cap).

Cap now discharges in a closed loop through both resistors. LHS of cap rises to +5V. RHS of cap falls to +5V.

Now ready for next switch closure.

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Initial Condition Vc=5V, but just after closure , 0V

Final condition Vc=0V after closed, transient response T=R2*C1 for 64% decay. Current on closure is limited to 5V/R2 on closure while R1 acts when open to discharge cap.

This is a differentiating negative edge pulse circuit.

Thus a sharp negative pulse to 0V with an exponential decay back to 5V.

If one wanted to limit the repetition rate of these pulses , increasing R1 to 10 Meg would result in only 10ms recharge T so a large cap xx uF for up to only a few seconds due to self leakage R.

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