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Turned out to be a lengthy question, please feel free to skip and go directly to the questions

Intro

I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to confusion regarding the actual data throughput capability. The project requires a read/write bandwidth of 250 MB/s. According to the datasheet on pages 3 & 7, the HyperRAM is capable of 400 MB/s, which should cover the needs of the project. Specifically I quote the following from page 7:

During a read (or write) transaction, after the initial data value has been output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequenced. When configured in linear burst mode, the device will automatically fetch the next sequential row from the memory array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data rate of 400 MB/s (1 byte (8 bit data bus) * 2 (data clock edges) * 200 MHz = 400 MB/s).

Use-case

My use-case scenario is to have a clock of 150 MHz, using linear data bursts. That would, theoretically, yield a bandwidth of 300 MB/s. Now according to section 9.5.4, a transaction should never last over Tcsm = 4 uS, which imposes a limit contrary to the above paragraph. Tcsm/Tclk = 600, so a transaction should not last over 600 cycles. This means that the actual bandwidth is now, considering a fixed 15 cycles config/access latency, (150M/600) * (600-15) * 2 = 292.5 MB/s, which is acceptable. It is convenient to transfer the data into 1 kB chunks, so instead of 600 cycles, a transaction is estimated as 512+15 = 527 cycles, which results in 291.6 MB/s, which is still acceptable and within time-frame.

Read Transaction Confusion

According to section 7.2:

Data will continue to be output as long as the host continues to transition the clock while CS# is Low. However, the HyperRAM device may stop RWDS transitions with RWDS Low, between the deliveries of words, in order to insert latency between words when crossing memory array boundaries.

Why is that? According to the introductory paragraph above, it should access simultaneously to provide a sustained data rate. Additionally, since I would like to transfer 1 kB of data, which is equal to a row size, does that mean that there will be no stalling since it will not cross a boundary? (presuming that a row is the only array boundary, and not a half page access)

Write Transaction Confusion

I am even more confused regarding write transactions. According to 7.3:

When data is being written and RWDS is Low the data will be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor the HyperRAM device is able to indicate a need for latency within the data transfer portion of a write transaction. The acceptable write data burst length setting is also shown in configuration register 0.

Data will continue to be transferred as long as the HyperBus master continues to transition the clock while CS# is Low. [..] Linear burst accepts data in a sequential manner across page boundaries.

I have a really hard time understanding that. Does that mean that the maximum burst size is the one configured in CR0? If so, maximum burst is 128 bytes, thus the maximum transaction cycles is 64+15 = 79, which is 243.03 MB/s. This is unacceptable for the project and way off what the introductory paragraph states. But thinking of it, it really makes no sense, since if this is the allowed burst size then Wrapped Burst is useless because you won't have more bytes to actually wrap around.

Now it gets even more confusing ins section 9.4.2, Table 12, where examples are given. In the first example, a Hybrid 128 is presented which clearly states that way more than 128 bytes are written while, in the last example, Linear Burst implies that you can write any length of data. So according to that, there is no Linear Burst limit.

Questions (TL;DR)

  • I would like to transfer data between host and HyperRAM in 1024 bytes chunks. Beside the Tcsm transaction limit, is there an additional Linear Burst size limit for read/write transactions? If so, what is it for each operation?
  • What is considered an array boundary?
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  • \$\begingroup\$ I think these are questions for Cypress / Spansion and the other vendors to answer. In other words, your question boils down to inter-transfer overhead for your bulk I/O cases. \$\endgroup\$ – hacktastical Apr 16 at 3:24
  • \$\begingroup\$ @hacktastical you are right, this question should be towards the vendor but in my experience companies tend to largely ignore individuals. I was hoping that someone here may have used this technology so could clarify matters a little bit. After all, these are relatively simple questions which should be straightforwardly answered by the datasheet. By the way, I looked at datasheets from other vendors and they all seem to be using the same, probably supplied by Cypress, so no new information can be extracted. \$\endgroup\$ – Mr.Y Apr 16 at 8:50
  • \$\begingroup\$ Make friends with your local FAE (field applications engineer) for Cypress/Infineon. \$\endgroup\$ – Kartman Apr 16 at 10:03

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