The wording may not be ideal, but it's rather simple.
If CE is high, the chip ignores OE and WE so it can't be read or written, and when CE is low the chip reacts to the OE and WE lines, so it can be sent read cycles or write cycles. But you can only do either a read cycle or a write cycle, as both simultaneously is invalid operation.
If the chip is being sent a byte of data with a write cycle, conrolled by WR and CS being low at the same time, the data bus must be an input so obviously the OE pin must be held high, as the data bus would be an output when OE pin is low with CE being low.
What it means that OE can be low at some points during the cycles, but it cannot be low during the write cycle when both CE and WE are low. No matter if it is the CE or WE that initiates the write, OE being low is enough to inhibit a write operation.