# Operation of a simple transistor capacitance multiplier

According to the text, due to the Zener diode, Q1 is supplied with a constant base voltage.

Any change in the output voltage is sensed at at the emitter of Q1 which brings a change in the forward bias of the transistor. Thus the transistor changes its resistance at the CE junction and compensates for the voltage change at output or input.

Here the transistor is acting as a variable resistor. The total current passes through the transistor hence it is also called a pass transistor.

Q1. What difference would it make if I replace this Zener diode with a capacitor and how would this circuit behave with a 1 Vp-p ripple superimposed on 5V DC input signal?

I have multiple queries regarding capacitance multipliers. I will take them successively.

Source article

Refer to figures 4.34, 4.35, and 4.36.

• I don't see any zener diode. Commented Apr 17, 2021 at 6:05
• That is a terrible source article. It contains many errors. For example, using a shunt regulator with no source impedance. Commented Apr 17, 2021 at 13:45
• You already have the circuit entered into a simulator -- what did it tell you? Hint: run the simulation longer than a few cycles of the AC source. In general, you should run a simulation for at least 3x the longest time constant in the circuit. In this case, the time constant of R1-C1 is 100 ms, so you should run the simulation for at least 300-500 ms to get a better feel for the overall behavior of the circuit. Commented Apr 17, 2021 at 14:12

The capacitance multiplication effect is related to how the capacitor discharges. Consider the following two circuits:

simulate this circuit – Schematic created using CircuitLab

When SW1 opens, C1 discharges through D1 and R1, with an initial current of $$\\frac{10 V - 0.65 V}{100 \Omega} = 93.5 mA\$$. This current discharges C1 within a certain amount of time, roughly half a second.

With the second circuit, when SW2 opens, the voltage across R2 and the current through it are the same as R1. However, because the transistor has gain — let's say that the β is 99 — 99% of that current comes from the collector, and only 1% comes from the base. Since the current flowing out of C2 is only $$\\frac{1}{100}\$$ the current flowing out of C1, it takes 100 times as long to discharge, on the order of 50 seconds. From the point of view of R2, it seems to be connected to a capacitor that is 100× the actual value.

All of this assumes that the collector of Q1 always has a higher voltage than its base. If the collector voltage drops too low because of excessive input ripple, then C2 will also dicharge through the base-collector junction, ruining the "capacitance multiplication" effect.

• @Dave..Its means maximum gain the better..If gain is less then, collector current decreases and current flowing via BE junction increases to reduce cap multiplication effect. A couple of queries..... 1.If a resistor in parallel (voltage divider bias) with C is used, cause base voltage Vb to reduce further. If Vb reduced but still lower than Vc (collector voltage), what effect does adding this resistor plays in the circuit. It strengthens multiplication effect.?? If yes then how? (Assuming Vb is sufficient to maintain 0.6 V drop across BE junction) Commented Apr 20, 2021 at 17:11
• contd....2.If Vb > Vc transistor is said to be saturated (fully ON). The collector current is high which is good for capacitance multiplication “but C2 will also discharge through the base-collector junction, ruining the "capacitance multiplication" effect.”?? 3. If gain goes down the current coming out of the base increases, thus reducing cap multiplication effect, mathematically, the effective value of cap = CXβ. How to derive this expression. Can I begin with normal KVL/KCL? Commented Apr 20, 2021 at 17:12
• I'm not sure where you're going with this. But another way to look at it is that from the point of view of the capacitor, the transistor multiplies the value of the load resistor. So you can easily calculate the effect of putting another resistor in parallel with that. You can use KVL/KCL only if you use the correct model for the transistor and keep in mind tie model's limitations and assumptions. Commented Apr 20, 2021 at 21:24

That is well known circuit in literature.

It has a limitation though:

The BJT Q1 is able to multiply the capacitance of C1 up to the cut-off frequency of Q1 itself.

Beyond the cut-off frequency of Q1, the transistor effect vanishes, and C1 won't be multiplied anymore.

The capacitance multiplier is a pretty rubbish name. It's just a buffered filter. The RC section you see is just a single pole low pass filter. Higher frequencies are filtered out. Assuming the load is large enough (Here the transistor acts as a buffer, but a 10ohm load is probably too small), the RC section will highly attenuate the output voltage. Of course as Enrico said, as the frequency increases, the transistor's ability to buffer decreases. After that you're on your own.

I have simulated the circuit with some other values:

R1=3.8k, R2=0.1k, C=1µF.

Result: First order lowpass with a gain below unity (app 0.8) and a 3db-cut-off which is app. at wc=1/CR1. No multiplication effect.

• How did you measure "multiplication effect", which is related to load ripple, not supply ripple? Commented Apr 18, 2021 at 17:46