The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA.

Intel MAX10 FPGA Datasheet

My question is, can we have 2 separate independent single ended clock signals being input into the FPGA on these two pins or just one single ended clock on either of them?

  • 1
    \$\begingroup\$ Which FPGA? Include a link to the datasheet. What does the datasheet say? \$\endgroup\$ Apr 19, 2021 at 10:10
  • \$\begingroup\$ Intel MAX 10 FPGA. intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/… \$\endgroup\$
    – gyuunyuu
    Apr 19, 2021 at 10:12
  • 1
    \$\begingroup\$ In the future, please add such important information into your question. And it's preferable to edit your question and add them there rather than via a comment. \$\endgroup\$
    – jwh20
    Apr 19, 2021 at 10:16

1 Answer 1


The guide you want is the "Intel Max 10 Clocking and PLL User Guide". This discusses the clock networks and PLLs including what inputs can be used for what.

To answer your question, yes in the Max 10's each differential clock input can also be used as two single ended inputs.

In the case of PLLs, either of the P and N pins can be used as a dedicated clock input - note that each PLL is specced for 2 differential inputs or 4 single ended inputs.

In the case of clock networks, the P and N pins drive different GCLK lines. This is generally not an issue as the synthesis tools take care of this, but if you have multiple clocks, it is generally best to double check in that user guide that all of your clocks can drive their own GCLK line.

  • \$\begingroup\$ Could you kindly refer me to the relevant section in the document so I can write it down :) Also, how do I check if a specific clock input can drive its own GCLK line? Isn't that supposed to be a case anyway? Or do you mean that a clock line may drive PLL input directly and not a GCLK directly? That should not be a problem if the routing can still link it to the GCLK anyway right? \$\endgroup\$
    – gyuunyuu
    Apr 19, 2021 at 10:55
  • \$\begingroup\$ @Quantum0xE7 each clock input can only drive a subset of the GCLK lines. I think though in these small devices there are few enough clock inputs that all dedicated inputs can be used at once. \$\endgroup\$ Apr 19, 2021 at 11:42
  • \$\begingroup\$ @Quantum0xE7 Description of both starts on page 5 (section 2) \$\endgroup\$ Apr 19, 2021 at 11:45
  • \$\begingroup\$ The table 2 shows what GCLK networks can be driven by which clock pin. Based on this, it gives me an impression that a single clock pin cannot drive logic in the entire device as it can only feed certain GCLK networks. Where is my understanding wrong about this? \$\endgroup\$
    – gyuunyuu
    Apr 19, 2021 at 12:29
  • \$\begingroup\$ @Quantum0xE7 the GCLK lines run through the entire device. \$\endgroup\$ Apr 19, 2021 at 12:56

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