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I'm learning ropes with STM32 and everything was going pretty well until...

I have STM32F469i-Discovery (Touch DSI 800x480, SDRAM, QSPI Flash etc.) Have ton of docs - datasheets, manuals, PCB schematic and so on.

So now I got to the stage where I need to interface SDRAM IC with FMC. I used STM32Cube_FW_F4_V1.26.1 collection of examples, specifically \STM32Cube\Repository\STM32Cube_FW_F4_V1.26.1\Projects\STM32469I-Discovery\Examples\FMC\FMC_SDRAM.

According to code comments/documentation, my SDRAM is executing this example script correctly (LEDs indicate all good). So it works. But I don't understand how and why.


So the datasheet of 469 clearly indicates

enter image description here

But when I use debugging and breakpoint, I find only garbage at address 0x60000800 (taking SDRAM offset into account). Instead, the correct values are under 0xC0000800, which is FMC Bank 5 as per datasheet.

main.c has

hsdram.Init.SDBank = FMC_SDRAM_BANK1;

at the same time, main.h has

#define SDRAM_BANK_ADDR                 ((uint32_t)0xC0000000)

My only question can be summarized as:

enter image description here

Can anyone give a reasonable explanation and/or provide a link which makes this clear as to why FMC bank 1 gets mapped onto FMC bank 5 addresses?

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  • \$\begingroup\$ The Reference Manual, page 304, section 12.4: Bank 4 and 5 used to address SDRAM devices (1 device per bank), and Figure 37 "FMC Memory Banks" quite clearly shows that SDRAM Bank 1 is located at 0xC0000000. I think you're confusing "FMC Bank 1" with "SDRAM Bank 1". \$\endgroup\$ – brhans Apr 19 at 15:15
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The board manual says this :

"The SDRAM is selected by SDNE0 and can be addressed from 0xC000 0000 to 0xC0FF FFFF."

The reference manual says only banks 4 and 5 support SDRAM, so there can be no SDRAM on bank 1.

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  • \$\begingroup\$ Thank you. Indeed important point. However: In Cube IDE in FMC Configuration it's fixed to SDRAM Bank 1 (dropdown menu with only option). From what I understand, my SDRAM is mapped to 0xC000 0000 (which it is), it's labeled as SDRAM Bank 1, but mapped to FMC Bank 5. Seems like an error/bug/oversight from STM. Is my statement correct? \$\endgroup\$ – Ilya Apr 19 at 14:26
  • \$\begingroup\$ Found that piece in the board manual. However, this conclusion doesn't follow at all from MCU datasheet or MCU reference manual itself. The only logical conclusion is that I'm missing or misinterpreting something. Which is exactly why I'm asking. (mismatch between FMC bank configuration and SDRAM bank configuration) \$\endgroup\$ – Ilya Apr 19 at 14:39
  • \$\begingroup\$ No, there is no contradiction anywhere in my opinion. The FMC supports two SDRAM banks, and thus SDRAM banks 1 and 2 (or 0 and 1 depending on how you count them) must be FMC banks 4 and 5. \$\endgroup\$ – Justme Apr 19 at 15:34
  • \$\begingroup\$ I think I understood, thank you \$\endgroup\$ – Ilya Apr 19 at 15:54

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