FPGAs have dedicated pins to input clock. They are supposed to directly connect to clock networks and PLL inputs. However, if we use a nondedicated pin, the design can still compile. Why are we allowed to compile a design that uses clock on nondedicated clock pins and what affects does it have on the design performance?

  • \$\begingroup\$ These are simply routed more efficiently to minimize the jitter. If you use non-dedicated, it might fail timing which would work otherwise. \$\endgroup\$ – Eugene Sh. Apr 19 at 14:18
  • \$\begingroup\$ Why should it fail timing? Due to clock insertion delay or what? \$\endgroup\$ – Quantum0xE7 Apr 19 at 14:31
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    \$\begingroup\$ Clock jitter and delay can affect the maximum frequency the design can work with. The clock needs to "feed" different parts of the FPGA, and if the clock edge is not coming to these parts "synchronously" enough - it affects the functionality. \$\endgroup\$ – Eugene Sh. Apr 19 at 14:35

The clock input pins have optimised routes to the clock distribution logic.

At worst this means lower delays compared to general purpose pins.

At best this means accurately constrained delays, that allow the clock PLLs to drive the clock nets with near zero skew from the clock input pins.

The tools generally don't forbid a design that uses GP pins as clock inputs, you may be forced for some reason to do that. However, your design will not be able to take advantage of all the optimisations that the dedicated pins can provide, so will probably be slower.

  • \$\begingroup\$ Check the manufacturer's website for documentation. I know that Xilinx documents this somewhere, either in an app note or in their data sheets. (Well, I know they did, the last time I looked, 20 years ago...). It's probably a good idea to check anyway -- I don't know if anyone does this, but it's certainly conceivable that dedicated clock inputs could be restricted to zones of the chip. \$\endgroup\$ – TimWescott Apr 19 at 14:58
  • \$\begingroup\$ Also, some chips preserve specific routing layers for clock signals – you might get into high-speed routing trouble once you try to do anything with that clock-converted-to-logic signal. \$\endgroup\$ – Marcus Müller Apr 19 at 16:32

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