FPGAs have dedicated pins to input clock. They are supposed to directly connect to clock networks and PLL inputs. However, if we use a nondedicated pin, the design can still compile. Why are we allowed to compile a design that uses clock on nondedicated clock pins and what affects does it have on the design performance?
The clock input pins have optimised routes to the clock distribution logic.
At worst this means lower delays compared to general purpose pins.
At best this means accurately constrained delays, that allow the clock PLLs to drive the clock nets with near zero skew from the clock input pins.
The tools generally don't forbid a design that uses GP pins as clock inputs, you may be forced for some reason to do that. However, your design will not be able to take advantage of all the optimisations that the dedicated pins can provide, so will probably be slower.