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An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate that I can run this at with the FPGA I have, assuming that the FPGA is the limiting factor.

These two FPGAs are being compared:

  1. Max 10

  2. IGLOO 2

I believe that I just need to look at the fastest rate that the FPGA I/O pins can be run at. But, obviously the FPGA fabric will also need some attention. How can I find a ball park figure?

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How can I find a ball park figure?

Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes.

Option 2: Gain sufficient experience with a particular product family to have a good idea how complex a design can be run at a given frequency.

That said, if the I/O pins can handle a given data rate, there are techniques such as parallelization that should allow you to handle that rate in the fabric, at the expense of increasing the number of logic blocks used.

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  • \$\begingroup\$ But what is the data rate possible on the I/O pins specifically, the logic fabric aside? \$\endgroup\$ – Quantum0xE7 Apr 20 at 14:21
  • \$\begingroup\$ @Quantum0xE7, It depends on IO standard, speed grade, etc. For example, the specs for LVDS are on page 53 in the MAX10 datasheet you linked to. \$\endgroup\$ – The Photon Apr 20 at 14:56
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The maximum clock for SRAM blocks of igloo 2 is 400MHz (Section 2.1.1 Product Brief) , and since many designs will use an SRAM block at some point, maybe that might be a good number to do a 'back of the napkin' calculation with that would give you a max number, the real number could be substantially lower than that.

But there is no way to tell unless you actually synthesize a design with clock constraints.

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    \$\begingroup\$ Oh, by the way if your investing in the future Altera has very little interest in maintaining relationships with small volume customers for their Max 10 line because of the Intel buyout. If I were choosing today, I would choose a lattice part over Altera. \$\endgroup\$ – Voltage Spike Apr 20 at 18:09
  • \$\begingroup\$ That's a very odd and unsubstantiated comment to make. And why do small volume customers need a 'maintained relationship' with a parts supplier. They need a supply of parts from a distributor, not a pal. The OP should evaluate their own commercial position, as they would for any supplier, rather than follow a rather wild hunch. \$\endgroup\$ – TonyM Apr 20 at 19:23
  • \$\begingroup\$ Because I lost my connection to their sales/support network and they've made their prices much higher for low volume customers. They used to have good prices on their FPGA's, the prices were raised significantly after the merger. And no, the comment is not unsubstantiated, because of the changes I decided not to use Max10's in my designs. \$\endgroup\$ – Voltage Spike Apr 20 at 19:38
  • \$\begingroup\$ It's unsubstantiated because you wrote a generalisation about what everyone will get, just from your own experience. That's not what I've seen, nor what I've heard from the variety of clients using Intel (Altera) parts in medium-volume, low-cost low qty and very high cost low qty manufacturing in commercial, defence, medical and automotive. Most of those have little need for 'maintained relationships' in their sales/support network - if you have a higher need for support then, again, that's very subjective. I've designed in plenty of their parts in those markets with no need to talk to them. \$\endgroup\$ – TonyM Apr 20 at 19:49
  • \$\begingroup\$ I was sharing my experience, and I never told anyone to choose one way or the other. I simply said "I would choose" Lattice over Altera/Intel. YMMV. I really wished I had never used Max 10 parts and invested any time into their toolset, that is my experience. If a company doubles their prices, that would make anyone reconsider their design. Max 10's used to be comparable in price to high end micro's, that ended shortly after the buyout. \$\endgroup\$ – Voltage Spike Apr 20 at 20:08

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