I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the image below. I suppose I should be able to deduce something from the T2.27.2 min/max timings but I'm stuck. Can anyone explain how are setup/hold times calculated from the image below?
Thanks a lot!