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I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the image below. I suppose I should be able to deduce something from the T2.27.2 min/max timings but I'm stuck. Can anyone explain how are setup/hold times calculated from the image below?

Thanks a lot!

DP83630 RMII Receive Timing

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  • \$\begingroup\$ These aren't setup or hold times, they're the delays on outputs changing state after the clock edge. \$\endgroup\$
    – Finbarr
    Apr 20 '21 at 14:48
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From the RXD line on the drawing, data goes invalid (grey) an undefined time after RXCLK, and becomes valid at T2.27.2 between 2 and 14 ns after CLK.

Thus there is no explicit spec on hold time; but it cannot reasonably change BEFORE the clock, so take hold time as 0.

Then setup time is simply the clock period minus the maximum data valid time, or T2.27.1 - max( T2.27.2)

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