Using the Cadence GPDK045, I generated the following plots of threshold voltage (left) and drain current (right) vs. body voltage for an NMOS device with 45nm channel length. As you can see, over a significant voltage range the threshold voltage actually decreases as \$V_{SB}\$ increases, resulting in increasing current over that range. This is contrary to what I thought to expect, which is that generally the threshold should increase with increasing \$V_{SB}\$.

Is it likely I made some kind of error in the simulation setup, or is this common for very short channel devices, or perhaps MOS devices in general?

In the simulation I fixed the gate-source and drain-source voltages to be equal at 1 V, so saturation is guaranteed.

enter image description here


1 Answer 1


Amazingly, even though I thought I checked it multiple times it turns out I really did just accidentally flip the polarity of what I thought was the \$V_{SB}\$ I was applying. Sorry for no big mystery here.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.