Using the Cadence GPDK045, I generated the following plots of threshold voltage (left) and drain current (right) vs. body voltage for an NMOS device with 45nm channel length. As you can see, over a significant voltage range the threshold voltage actually decreases as \$V_{SB}\$ increases, resulting in increasing current over that range. This is contrary to what I thought to expect, which is that generally the threshold should increase with increasing \$V_{SB}\$.
Is it likely I made some kind of error in the simulation setup, or is this common for very short channel devices, or perhaps MOS devices in general?
In the simulation I fixed the gate-source and drain-source voltages to be equal at 1 V, so saturation is guaranteed.
