# How to calculate the bandwidth of a synchronous bus with overlap in bus transfer and reading next data?

I am working through problems in Saylor Academy's computer architecture course. I can't understand how this kind of problem is solved:

Consider a 32-bit synchronous bus with f = 125 Mhz, an 8 nsec clock cycle (CK), send address/data takes 1CK each, 2CKs between bus operations, a memory access time of 200 nsec, bus transfer and reading next data overlap, block size 8 words. What is the bandwidth for 256 4-byte words to be transferred across the bus?

The given solution:

The BW calculation is as follows: 256/8 blocks gives 32 total transactions. Each memory access takes 200/8 = 25 clock cycles. Send data/address + idle time is 8 clock cycles for a total of 34 clock cycles including 1 clock cycle for the initial memory read.....

I could not understand this:

Send data/address + idle time is 8 clock cycles

I expect that it would be 1 cycle for send data, 1 cycle for send address and 2 cycles idle time, for a total of 4 cycles. Why is one cycle required for the initial memory read?