I am working through problems in Saylor Academy's computer architecture course. I can't understand how this kind of problem is solved:

Consider a 32-bit synchronous bus with f = 125 Mhz, an 8 nsec clock cycle (CK), send address/data takes 1CK each, 2CKs between bus operations, a memory access time of 200 nsec, bus transfer and reading next data overlap, block size 8 words. What is the bandwidth for 256 4-byte words to be transferred across the bus?

The given solution:

The BW calculation is as follows: 256/8 blocks gives 32 total transactions. Each memory access takes 200/8 = 25 clock cycles. Send data/address + idle time is 8 clock cycles for a total of 34 clock cycles including 1 clock cycle for the initial memory read.....

I could not understand this:

Send data/address + idle time is 8 clock cycles

I expect that it would be 1 cycle for send data, 1 cycle for send address and 2 cycles idle time, for a total of 4 cycles. Why is one cycle required for the initial memory read?

  • \$\begingroup\$ Please expand the solution quote to include the first word of the next sentence. \$\endgroup\$
    – greybeard
    Dec 18, 2022 at 11:07
  • \$\begingroup\$ Does the solution mention explicitly where bus transfer and reading next data overlap? \$\endgroup\$
    – greybeard
    Dec 18, 2022 at 11:08

1 Answer 1


A word is assumed to be 1 byte. The bus is 32-bits wide. To transfer 8 words i.e. 64 bits, it needs 2 send data and send address operations.

So it will be 2 x (1 cycle for send data + 1 cycle for send address + 2 cycles idle time) = 2 x 4 = 8 cycles

One additional cycle for the additional memory read is required because during the first cycle, bus transfer can't be overlapped with reading next data.

  • \$\begingroup\$ 8 words i.e. 64 bits from the question: 4-byte words: word size = bus width = 32 for 256 bits/block. \$\endgroup\$
    – greybeard
    Dec 18, 2022 at 10:17

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