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I have implemented multiplier by using IP catalog and added in simualtion as

COMPONENT gen_mult
  PORT
    (
    CLK :                               IN  STD_LOGIC;
    A :                                 IN  STD_LOGIC_VECTOR(10 DOWNTO 0);
    B :                                 IN  STD_LOGIC_VECTOR(10 DOWNTO 0);
    P :                                 OUT  STD_LOGIC_VECTOR(19 DOWNTO 0)
  );
  END COMPONENT;

I am going to use N - multiplier, where N is a number of filter coefficients.


   mult_d_comput:
  for i in 0 to N_coeff-1 generate
      mult  : gen_mult port map
                (
            CLK =>                  clock,
            A =>                    pipel_data(i),
            B =>                    h(i),
            P =>                    product(i)
            );
  end generate mult_d_comput;

My question is :

The P (product / output of IP) is defined as 20 bit std_logic_vector. Why is the esult of product from loop 20 bit std_logic_vector ?

I have thought it should be std_logic_vector ( ( ( width_pipel_data+ width_h+ log2(number_filter_coeff) -1 ) downto 0)

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  • \$\begingroup\$ Ha ? How come number of filter coefficients will ever determine the output width? It determines only the number of instances of the multiplier, as per your vhdl description. \$\endgroup\$
    – Mitu Raj
    Commented Apr 22, 2021 at 11:09

1 Answer 1

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Because your gen_mult component has a 20 bit output (and two 11 bit inputs, weird..), and I assume you have defined the product as an array of 20 bit words, what else should it be?

If you want a longer output you need to say so, and probably also actually sum the products together at some point?

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  • \$\begingroup\$ 20 bit output (and two 11 bit inputs, weird..) until you think one sign bit each \$\endgroup\$
    – greybeard
    Commented Jan 27 at 21:42

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