First at all, thank you so much for all the answers I have received on all the threads. Well, I'm working on PCB Raspberry Compute Module 4 Carrier including USB 3.0 Controller (TUSB7320) using PCIE lines. I have inspected this layout guide:
But It create some doubts about priorities of rules. TI recommends reduce the number of vias and reduce the length of the traces. What is the stronger rule? In the first picture I avoid using more vias incrementing the length (much less than the maximum length that TI recommends). What is better?
On this picture I can't use narrower traces (I would need 0.10 mm width trace to put the trace between pads) so the number of vias is not equal for these two lines. Should I to create 2 vias to change the layer and matching the length for the two layers?