In short, yes, this is possible.
Since you need to toggle twice in that period, you need to count up to the number of cycles the input clock would do divided by two, between the two clock toggles.
So, you could just replace your
2500000 constant with something else. That something else would likely be
1_199_904. One nice thing VHDL lets you do is that you can make your numeric literals more legible by introducing underscores where you want stuff to be spaced out.
However, this is AFAIK not the best practice for generating slow "clocks". You probably might want to think of it as triggering events at a longer interval instead. (TODO: explain why.)
See perhaps this answer to learn more.
Basically, what you'd do instead of
-- your magic that happens every clock period, ie. 50x a second
is something like this:
if(rising_edge(clk_fast) and enable_50Hz) then
-- your magic that happens every enable period, ie. still 50x a second
A convenient way of generating these signals may be perhaps something like this:
entity enable_timer is
divide_by : integer := 5_000_000
clk : in std_logic;
srst : in std_logic; -- sync reset
enable : out std_logic
end entity enable_timer;
architecture I_took_this_from_stackexchange of enable_timer is
signal counter : integer := 0;
magic: process(clk) is
enable <= '0';
if(srst = '1') then
counter <= 0;
elsif(counter >= divide_by) then
counter <= 0;
enable <= '1';
counter <= counter + 1;
end architecture I_took_this_from_stackexchange;
You could instantiate this with a
generic map mapping the
divide_by parameter to whatever suits your needs at any particular moment (like
2_399_808 to get your 41.67Hz out of your 100MHz clock), and you'll almost* never have to write this timing's entity's implementation again! Reuse it for all your slow* timings! Amazing, isn't it.
An example for instantiation, for the sake of completeness:
generic map (count_to => 2_399_808)
port map (
clk => clk_100MHz,
srst => reset, -- or '0' if not used
enable => enable_41_67Hz
With a counter like this, you can generate about any frequency with 1-period of your main clock resolution, that is 10ns resolution for your 100MHz clock. So yes, 41.67Hz is doable, with about 0.024% error in this case. You can get this constant by dividing the frequency of the input clock and the output clock and rounding. The error comes from exactly this rounding.
*) The error may not always be this low, for example when the output frequency is much closer to the main clock's frequency, and it does not divide quite cleanly. In those cases you could use a fractional clock divider of some sort. I'll say those are beyond the scope of this answer. :)
I have not actually checked the syntax of the above examples yet, so take them more as a guidance than a straight-up copy-pasta.