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I have wrote a FIR filter in VHDL by using ISE design suit. In design summary I can get all information about the timing analysis.

There is information about the max frequency.

enter image description here

and I have also found information about gate delay.

What does minimum period( max frequency) mean for filter realisation?

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    \$\begingroup\$ @user_1818839, improve the pipelining or use a faster FPGA part. \$\endgroup\$
    – TonyM
    Commented Apr 22, 2021 at 13:07
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    \$\begingroup\$ @TonyM when it's this bad, a faster FPGA won't be much help. Sure, if you get 80MHz and need 100MHz for example, that's an option. \$\endgroup\$
    – user16324
    Commented Apr 22, 2021 at 15:17
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    \$\begingroup\$ @user_1818839, oh yes it will, make a huge difference, far more than +25%. For example, if you have a MAX 10 or iCE40 and switch to a Virtex-7 or UltraScale, you'll find a huge speed difference. And there's loads of parts between and around those extremes. We don't know what the OP is using but my statement stands, whatever FPGA they have as it's clearly not top-end. \$\endgroup\$
    – TonyM
    Commented Apr 22, 2021 at 15:26
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    \$\begingroup\$ @TonyM I thought you were referring to speed grades. Sure you could replace a $10 Spartan-6 with a $1000 Ultrascale and get several times the speed, but that's still the wrong answer for something as basic as an FIR filter running as glacially slow as 11 MHz. \$\endgroup\$
    – user16324
    Commented Apr 22, 2021 at 18:11
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    \$\begingroup\$ In a modern FPGA, 86MHz is pretty slow and I'd be looking for architectural improvements IF it didn't meet my goal... In a Spartan-3 it would be reasonable. \$\endgroup\$
    – user16324
    Commented May 17, 2021 at 12:02

1 Answer 1

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Your filter is a synchronous design with a clock. Assuming you have provided the timing constraints correctly, the minimum clock period or the maximum clock frequency is the maximum frequency (as reported by the Synthesiser) at which you can clock your design and guarantee reliable operation (ie., with no timing violations) on the FPGA you have chosen.

Beyond this clock frequency, the operation of your design is not guaranteed to be reliable, as it may cause timing violations.

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  • \$\begingroup\$ frequency , about 86 Mhz, is it still slow filter? \$\endgroup\$
    – Jang Lee
    Commented May 17, 2021 at 11:59
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    \$\begingroup\$ Report says 86 ns or 11 MHz. That's slow for digital filter. \$\endgroup\$
    – Mitu Raj
    Commented May 17, 2021 at 12:16
  • \$\begingroup\$ Minimum period: 11,613ns (Maximum Frequency: 86,110MHz) ( my result). How to improve it? \$\endgroup\$
    – Jang Lee
    Commented May 17, 2021 at 13:52
  • \$\begingroup\$ You should ask it as separate question. Not in comments. Besides you don't acknowledge the answers given by this community by not accepting answers and as well as you delete the questions once someone answer it. Which is not a welcoming behaviour here. \$\endgroup\$
    – Mitu Raj
    Commented May 17, 2021 at 15:07

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