I am using this power supply shown in the datasheet here: RS-D3305P Datasheet

Channel 1 is set to 26V, channel 2 is 5V and channel 3 is set to 3.3V. All the negatives are joined together.

Channel 3 is only used to power an ADC chip (AD7476A) and a pot circuit as the analog input. I have been having trouble getting any decent results from this ADC chip and was starting to wonder if the power supply was noisy. In the datasheet it shows the channel 3 has a load regulation of +-50mV. Is this a bad power supply to power an ADC with?

I am measuring 5mV at the input ADC but reading around 65. Maybe the power supply is adding ripple to it? could be an issue with the timing signals but would like to check out the power supply first.

Note, the ADC chip is 12 bit and the ADC analog input voltage is 3.3V

Below is an schematic for the hardware circuits:


Below is an image of the physical hardware circuit, which is built temporary:

Hardware Image

Below is an image of the noise on the ADC input waveform:

ADC Voltage Waveform

Below is an image of of the ADC input voltage waveform in yellow, and the 3.3V in blue:

ADC voltage vs Power supply Voltage waveforms


So I got a perf board soldered up today with the old circuit along with the modifications that has been recommended here in this forum. Honestly I can not believe the difference! The ADC value on the display now flickers at most by 2 bits. Even without any software filtering I can turn the pot to get any value on the display, with one or two at most LSBs of flicker, and at times there is no flicker! I am very happy with the results and can't thank everyone that posted here enough. I will try to summarise my modifications with some pictures to try and help other beginners like myself:

  1. Got rid of the breadboard and soldered the circuit onto some perfboard (I think it is called, see image below). Having soldered traces on the perfboard instead of long flying wires seems to make a massive difference. I tried to follow a start point ground as best I could. It is the node with all the connections in the top left on the bottom of the board.

  2. Tried my best with my limited analog knowledge to separate the analog traces and digital high speed traces by routing them away from each other. Although don't worry just as much about this (obviously don't cross over each other or this probably does matter if you are using a 24-bit ADC lol). When I had the last line which happened to be the SCLK, I ended up having to run it adjacent to the ground trace which isn't recommended, but still seems to work.

  3. I added lots of capacitors, both electrolytic and ceramics across all IC supplies, the ADC pin and the potentiometer wiper. I kept them as close to the Vdd or positive connection for each device. I followed the datasheet for the ADC chip for the decoupling capacitor size, but the rest were just hand picked with whatever I had to be honest.

  4. I added 330 ohm source resistors for the CS and SCLK on the FPGA output pins, and a 330 ohm source resistor on the SDATA right beside the pin on the ADC. The seem to help massively.

  5. I still have flying wires from the ADC chip to the FPGA which you can see below in the pictures, but they are twisted and wrapped in tin foil and they seem noise free, honestly! Touching them has no effect on the ADC output.

  6. Added a 330 ohm resistor directly across the 3.3V supply as was suggested to put a constant small load on the power supply in an attempt to improve it's regulation. Don't know if it made a difference to be honest, but doesn't do any harm. I won't be removing it anyway.

Note, there are different potentiometers used in the pictures, I decided to change it to one with screw connections just. I will post the complete modified schematic tomorrow.

Thanks once again, without this forum I wouldn't have been able to do this, and learn what I have learned.

Below is the top side of the ADC board:

Top side of ADC board

Below is the bottom side of the ADC board:

Bottom side of ADC board

Below is an image of the board, FPGA and connections:

Overview of FPGA, ADC and connections

  • \$\begingroup\$ Can you post the schematic for the ADC circuit as well as an image of the circuit layout? An easy way to see if it is the power supply is to look for common mode noise. Show traces of both the power supply output and the ADC input. \$\endgroup\$ Commented Apr 22, 2021 at 18:40
  • \$\begingroup\$ @ScienceGeyser Posted schematic and hardware image. Will check for common noise now. \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 18:52
  • \$\begingroup\$ I am thinking the power supply maybe isn't the problem by the looks of it? \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 19:08
  • \$\begingroup\$ Can you add a trace with the 5V power as well? AC couple your inputs so you can put all scope signals at the same scale. I would suggest that you also try to clean up the breadboard wiring and make sure that your decoupling caps are physically as close as possible to the circuit chips. Long looping wires are going to be problematic for noise. \$\endgroup\$ Commented Apr 22, 2021 at 19:50
  • \$\begingroup\$ See edit to question. \$\endgroup\$
    – David777
    Commented Apr 23, 2021 at 22:03

3 Answers 3


Problem: no decoupling on power supply.

Solution: solder a capacitor on the ADC SMD adapter, preferably >100µF with ESR below 1 ohm. Clip the leads as short as you can. LM358 would also need one, any electrolytic will do. You could use ceramics, but since the power supply is quite far away, you'd need a large value to compensate for the wiring inductance, and you already have electrolytic caps in stock.

Problem: SPI in flying wires.

I see 3 SPI wires, with no ground return, so the high frequency digital currents return through the wires to the power supply, which means the bits will fall off and you will get wrong readings. So you should add a ground wire between the ADC and the FPGA, twist everything together, and slow down the SPI clock a lot, and add source resistors on all outputs to slow down the edges, something ridiculous like 330R-1 kOhm, until you get clean edges on all signals on the scope.

Personally I wouldn't use a solderless breadboard to experiment with your ADC. SPI in flying wires is always going to be a problem. However, it is absolutely possible to send 5ns rise time signals in handcrafted wires... if they are taped on a ground plane and source terminated. Note 50MHz SMD oscillator dumped in the middle of the board, no problem.

enter image description here

Problem: power supply noise

I's difficult to know what causes this without further tests, but you could remove the ADC from the breadboard and measure the power supply noise and ripple with the scope. You can also add a dummy load resistor to draw say 10mA on 3V3, see if that improves it. Some power supplies kinda go to sleep (ie, loss of transconductance in the pass device decreases open loop gain, which worsens regulation) when the load is too low and thus voltage ripple increases. But it could just as well be noise from the FPGA coupling through the flying wires. So you should experiment, also disconnect the FPGA, start from blank slate and add each part back, see when the power supply misbehaves.

  • \$\begingroup\$ Brilliant, thank you so much. I will try some of this out tomorrow and see if it makes any improvement. It makes a lot of sense. \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 21:40
  • 1
    \$\begingroup\$ Hehe, thanks. But you have several problems, this weird noise on the power supply, and also the SPI bus in flying wires, which will not work. \$\endgroup\$
    – bobflux
    Commented Apr 22, 2021 at 21:41
  • \$\begingroup\$ Yeah clocking at 16MHz first time using a serial chip maybe not a great idea. This is why I haven't got a motorbike, I'd be down the road at 150mph first day out haha. EDIT: What clock frequency do you recommend? \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 21:47
  • \$\begingroup\$ Look at the digital signal on the oscilloscope, if it looks like a squiggly mess with lots of ringing, slow down the edges by adding resistors in series with the source (I mean on the driver side of the wire), then adjust frequency accordingly. But you need that ground wire. \$\endgroup\$
    – bobflux
    Commented Apr 22, 2021 at 21:50
  • \$\begingroup\$ " and add source resistors on all outputs to slow down the edges, something ridiculous like 330R-1 kOhm, until you get clean edges on all signals on the scope." Sorry, do only add these resistors on the ADC side of SDATA and the FPGA side of SCLK and CS? All the same value? \$\endgroup\$
    – David777
    Commented Apr 23, 2021 at 11:58

You have a couple of decoupling capacitors on Vdd. But on the breadboard, they are not connected closely to the ADC. They may be more effective connected straight into the breadboard strip next to the DAC's Vdd.

  • \$\begingroup\$ Right that actually makes sense, I am pretty new to this. I have a 100nF arriving tomorrow which is recommended, so hopefully it will help. \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 20:36
  • \$\begingroup\$ See edit to question. \$\endgroup\$
    – David777
    Commented Apr 23, 2021 at 22:04

Since the ADC is an unbalanced input type, and referencing itself internally to the Vdd power, I would recommend powering everything off the 5V power supply. Because any difference of noise between the two power supplies will always show up in the signal because of this.

  • \$\begingroup\$ The only reason I power the ADC chip with 3.3V is because the FPGA I/O are 3.3V, so I can connect them directly. \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 19:15
  • \$\begingroup\$ If interfacing is an issue, you could either voltage divide the output or use 1K resistors with a reverse biased diode connected to 3.3V to clamp the high to 3V when the logic goes high. \$\endgroup\$ Commented Apr 22, 2021 at 19:24
  • \$\begingroup\$ Would this cause issues with the clock and data wires when switching? The SCLK is the fastest signal at 16.7MHz. \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 19:26
  • \$\begingroup\$ SCLK wouldn't need to be clamped just the SDATA out or in other words, the digital out. you use high speed switching diodes like BAS70-5 that is in the picoseconds of switching time \$\endgroup\$ Commented Apr 22, 2021 at 19:36
  • \$\begingroup\$ Yeah I suppose actually. The data sheet for the ADC shows 2.4V as the minimum voltage for a high level input so 3.3V directly should be fine. Yeah, I see, the SCLK and CS are inputs anyway so 3.3V is perfectly fine. Are you saying that this is the problem to the poor ADC readings? \$\endgroup\$
    – David777
    Commented Apr 22, 2021 at 19:40

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