I am building an automatic gain control for a subMHz signal, which comes in the 30-120mVpp range, using a NMOS as VCR. At the output, ideally, signal should be 'compressed' around +-Vpeak_detect_th . I decided to use a NMOS instead of the several circuits using NJFETs I have seen around, like in this circuit ( https://www.engineersgarage.com/circuit_design/circuit-design-automatic-gain-control/) because I can save an inverter stage in the peak detector.

After this, a High gain amplifier is used together with a peak detector at its output that controls the Vgs swing. With bias_mosfet I set the Vgs at Vgs(th) and the control signal is positive 0-800mV. So far is working good in simulation, with proper adjusting of the bias and the ratio_resistor/amp_gain balance. The problem I see is that this is designed assuming that Vgs(th) is fixed but thats not the case for real transistors, which have dispersion.

For the nFET circuits a usual practice is to add a feedback network so the gate gets Vds/2 to improve linearity.

What would be a way to mitigate the NMOS Vgs(th) dispersion in this curcuit? Without having to adjust the bias per circuit in fab?

Which NMOS is better for this application? Enhanced? Depletion?

As of now I am using 2N7002W From On Semi, which meets 2 important criteria, cost and smt.

Any suggestion on real parts? enter image description here


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.